Patents by Inventor Dave Scott Ebsen
Dave Scott Ebsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12334153Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.Type: GrantFiled: September 9, 2022Date of Patent: June 17, 2025Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
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Publication number: 20250013382Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.Type: ApplicationFiled: September 24, 2024Publication date: January 9, 2025Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
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Publication number: 20240393980Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Patent number: 12131060Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.Type: GrantFiled: July 25, 2022Date of Patent: October 29, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee
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Publication number: 20240347128Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
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Publication number: 20240302999Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: ApplicationFiled: April 30, 2024Publication date: September 12, 2024Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Patent number: 12079517Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: GrantFiled: July 21, 2022Date of Patent: September 3, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Patent number: 12068034Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.Type: GrantFiled: August 30, 2022Date of Patent: August 20, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick, Akira Goda, Jeffrey S. McNeil, Umberto Siciliani, Daniel J. Hubbard, Walter Di Francesco, Michele Incarnati
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Patent number: 12051479Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: GrantFiled: July 25, 2022Date of Patent: July 30, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
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Patent number: 12001721Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: GrantFiled: August 5, 2022Date of Patent: June 4, 2024Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Publication number: 20240087651Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.Type: ApplicationFiled: September 9, 2022Publication date: March 14, 2024Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Akira Goda, Dung V. Nguyen, Giovanni Maria Paolucci, James Fitzpatrick, Eric N. Lee, Dave Scott Ebsen, Tomoharu Tanaka
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Publication number: 20240071510Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Kishore Kumar Muchherla, Huai-Yuan Tseng, Giovanni Maria Paolucci, Dave Scott Ebsen, James Fitzpatrick, Akira Goda, Jeffrey S. McNeil, Umberto Siciliani, Daniel J. Hubbard, Walter Di Francesco, Michele Incarnati
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Publication number: 20240045616Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.Type: ApplicationFiled: August 5, 2022Publication date: February 8, 2024Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
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Publication number: 20240029815Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
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Publication number: 20240028259Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
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Publication number: 20240028252Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Inventors: Kishore Kumar Muchherla, Dung V. Nguyen, Dave Scott Ebsen, Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Akira Goda, Eric N. Lee