Patents by Inventor Dave Trossen

Dave Trossen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7889530
    Abstract: A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: February 15, 2011
    Assignee: Agate Logic Inc.
    Inventors: Robert Yu, Dave Trossen, Jack Liu, Mukunda Krishnappa, Kevin James
  • Patent number: 7557605
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: July 7, 2009
    Assignee: Cswitch Corporation
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James
  • Publication number: 20090077308
    Abstract: A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module is configured to generate a first auxiliary matchvector based on the first matchvector; and a first priority encoder (PE) operatively connected to the first IMR module, where the first PE is configured to output a first encoded memory address based on the first auxiliary matchvector, where the first CAM, the first IMR module, and the first PE are associated with a first reconfigurable content-addressable memory (RCAM).
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: Cswitch Corporation
    Inventors: Robert Yu, Dave Trossen, Jack Liu, Mukunda Krishnappa, Kevin James
  • Publication number: 20090072858
    Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: CSWITCH CORPORATION
    Inventors: Godfrey P. D'Souza, Douglas Laird, Malcolm J. Wing, Colin N. Murphy, Dana L. How, Robert Yu, Jay B. Patel, Ivo Dobbelaere, Jason Golbus, Suresh Subramaniam, Mukunda Krishnappa, Pohrong R. Chu, Dave Trossen, Kevin James