Abstract: A system for capturing aerial images, the system comprising at least one camera unit, the camera unit comprising at least one overview camera, a plurality of detail cameras, and a frame for holding the cameras, each detail camera having a longer focal length than the at least one overview camera, each detail camera mounted at a different angle laterally so that the fields of view of the detail cameras overlap to form an extended lateral field of view.

Abstract: A system for capturing aerial images, the system comprising at least one overview camera, a plurality of detail cameras, and a frame for holding the cameras, each detail camera having a longer focal length than the at least one overview camera, each detail camera mounted at a different angle laterally so that the fields of view of the detail cameras overlap to form an extended lateral field of view, the frame attachable to the floor of an aircraft above a camera hole, thereby providing the cameras with a view of the ground below the aircraft through the camera hole.

Abstract: A shipping container load securer including a pallet and a box connected to the pallet and filled with a filler, wherein the pallet and the box are substantially the same size and shape as a standardized crate used to package goods for transport in shipping containers. The load securer fills voids in partially filled shipping containers, enabling the shipping container to be tightly packed and preventing the movement of goods-filled crates during transport to minimize damage to the goods in the crates in the shipping container, while not substantially increasing the weight of the container.

Abstract: A regulatory compliance testing system permits a gaming machine (30-44) at a first location (14-20) to be tested for regulatory compliance with casino system software (44a,46) located at a second location (12) in a different jurisdiction. A plurality of different casino systems (46) can be kept at the second location (12) and each is associated with one specific port (54b-54e) at the first location so that each different type or model of gaming machine (14-20) has its own home port (54a-54e). A secured VPN Layer 2 network (24a-24e) including multisystem isolation made possible by VLAN (26a-26e) tunnels connects both locations and permits seamless and secure connectivity as if the gaming machine (30-44) and its associated accounting software (46) were located at the same location. The system (10) permits three (3) basic modes of testing. First, the gaming machine (30-44) may be tested at the first location (14-20) by an engineer at the first location (14-20).

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for modifying glyphs. In one aspect, a method includes receiving a glyph outline for a glyph to be rendered, the glyph to be rendered being associated with a character of a particular font and at a specified scaled size, the glyph to be rendered having one or more horizontal stems; identifying a darkening amount to be applied to the one or more horizontal stems of the glyph; modifying hints of the one or more horizontal stems of the glyph outline using the identified darkening amount to modify the glyph outline; and rasterizing the glyph using the modified glyph outline.

Abstract: Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.

Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.

Abstract: A processor includes primary threads of execution that may simultaneously issue instructions, and one or more backup threads. When a primary thread stalls, the contents of its instruction buffer may be switched with the instruction buffer for a backup thread, thereby allowing the backup thread to begin execution. This design allows two primary threads to issue simultaneously, which allows for overlap of instruction pipeline latencies. This design further allows a fast switch to a backup thread when a primary thread stalls, thereby providing significantly improved throughput in executing instructions by the processor.

Abstract: A regulatory compliance testing system permits a gaming machine (30-44) at a first location (14-20) to be tested for regulatory compliance with casino system software (44a,46) located at a second location (12) in a different jurisdiction. A plurality of different casino systems (46) can be kept at the second location (12) and each is associated with one specific port (54b-54e) at the first location so that each different type or model of gaming machine (14-20) has its own home port (54a-54e). A secured VPN Layer 2 network (24a-24e) including multisystem isolation made possible by VLAN (26a-26e) tunnels connects both locations and permits seamless and secure connectivity as if the gaming machine (30-44) and its associated accounting software (46) were located at the same location. The system (10) permits three (3) basic modes of testing. First, the gaming machine (30-44) may be tested at the first location (14-20) by an engineer at the first location (14-20).

Abstract: A modular power supply that can be adapted to receive and charge practically any type or number of portable electronic devices includes a power converter that receives an AC wall voltage and converts the wall voltage to DC bus voltage. Each charging module has a pair of conductive rails and magnets positioned around the exterior of the module. The power converter has a connector that is physically and electrically coupled to a charging module through a pair of magnets and conductive rails such that the DC bus voltage is applied to the conductive rails of the module. Each charging module has a dock that physically couples to a portable electronic device and supplies a charging voltage produced from the DC bus voltage to the device. Additional charging modules can be physically and electrically coupled together by simply placing the modules adjacent one another through the interaction of the module's conductive rails and magnets.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for improved techniques for executing instructions in a pipelined manner is provided. Such techniques may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed execution pipeline unit having a first and second pipeline, wherein the second pipeline is configured to execute instructions in a common issue group in a delayed manner relative to the first pipeline, and circuitry. The circuitry is configured to determine if a first instruction being executed in the first pipeline modifies data in a data register which is accessed by a second instruction being executed in the second pipeline, and if the first instruction being executed in the first pipeline modifies data in the data register which is accessed by the second instruction being executed in the second pipeline, forward the modified data from the first pipeline to the second pipeline.

Abstract: A method and apparatus for accessing a processor cache. The method includes executing an access instruction in a processor core of the processor. The access instruction provides an untranslated effective address of data to be accessed by the access instruction. The method also includes determining whether a level one cache for the processor core includes the data corresponding to the effective address of the access instruction. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address. If the level one cache includes the data corresponding to the effective address, the data for the access instruction is provided from the level one cache.

Abstract: Methods and apparatus implementing and using techniques for scaling a character having stems. A character including stems and having an associated output resolution and an associated bit depth can be received. The counters defined by the stems can be grouped into one or more chains of counters. The stems of the character can be aligned based on a stem alignment policy while the chains of counters are balanced based on the output resolution. A pixel map can be created at the output resolution and the output bit depth based on the aligned stems.

Abstract: Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted.

Abstract: A diaphragm actuator for a fluid process control device comprises a housing, a diaphragm, a stem, and a plate assembly. The plate assembly includes a concave plate and a convex plate, each having inner and outer radial portions. The outer radial portions compressingly engage and retain the diaphragm. The inner radial portions are compressed together onto the stem between a shoulder of the stem and a nut threaded onto the stem. Accordingly, the concave plate forcibly engages and provides a fluid-tight seal directly with the shoulder of the stem without requiring an o-ring or any other additional sealing component. Moreover, the concave and convex plates are structurally equivalent such that the actuator may easily be switched between a biased-open configuration and a biased-closed configuration.

Abstract: Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be maximized while processing bandwidth required to store vector data misaligned is minimized. Furthermore, embodiments of the invention provide logic within the load data path which allows vector data which is stored misaligned to be aligned as it is loaded into a vector register. By aligning misaligned vector data as it is loaded into a vector register, memory bandwidth may be maximized while processing bandwidth required to align misaligned vector data may be minimized.