Abstract: An aspect of the invention relates to a method of dynamically adjusting power consumption of a random access memory (RAM) coupled to a processor. Frequency of a memory clock signal coupled to the RAM is reduced. At least one supply voltage coupled to the RAM is reduced. At least one latency parameter of the RAM is configured in response to the reduced frequency and the reduced at least one supply voltage. The RAM may then be re-initialized. In this manner, voltage supplied to the RAM is reduced, thereby reducing power consumption in the RAM.

Abstract: A system for testing a printed circuit board assembly (PCBA), in accordance with embodiments of the present invention, includes an interface diagnostic module coupled to a multi-dimensional search module. The multi-dimensional search module performs a simultaneous switching output pattern based stress test for each of a plurality of sets of timing parameters. The interface diagnostic module determines an error rate on an interface of the printed circuit board assembly for each of the stress tests. The multi-dimensional search module determines a best set of timing parameters based on the determined error rates.