Abstract: The present invention, generally speaking, provides for a non volatile memory cell requiring no extra process steps. In one embodiment, the non volatile memory cell is a lateral polysilicon programmable read only memory cell, in particular a lateral poly fuse memory cell. Technique are provided to achieve a high yielding, voltage, temperature, and process insensitive lateral poly fuse memory. In one embodiment, a fusible link memory circuit includes a fusible link memory element and a programming circuit. The programming circuit includes a replica of the fusible link memory element and a programming current source for producing a known current density in the fusible link memory element in spite of variations including at least process variations.

Abstract: A bifurcated stent includes a first stent section and a second stent section. The first stent section is balloon expandable, has an unexpanded configuration, an expanded configuration, and a tubular wall defining a secondary opening. The secondary stent section is self-expanding and an end of the secondary stent section is engaged to a portion of the tubular wall of the primary stent section defining the secondary opening. The secondary stent section has an unexpanded configuration with a first length and an expanded configuration with a second length where the first length is less than the second length. The secondary stent section is expanded to the expanded configuration after the primary stent section is expanded to the expanded configuration. The secondary stent section forms a portion of the tubular wall of the primary stent section in the unexpanded configuration.

Abstract: Systems for delivering a bifurcated stent to a bifurcation site comprise catheters and/or bifurcated stents delivered therefrom.

Abstract: A bifurcated stent comprises a first stent section and a second stent section. Each stent section is expandable from a predeployed state to a deployed state independently from one another. The second stent section having an end engaged to a receiving region of the first stent section. In the deployed state the first stent section defines a primary flow path and the second stent section defines a secondary flow path in fluid communication with the first flow path. At least a portion of one or both the first stent section and second stent section is constructed from a wire member.

Abstract: According to the invention there is provided a system for supporting fixtures such as birdhouses, lanterns and feeders from differentiated supports. The apparatus includes a mounting board having front and back major surfaces. At least a first and preferably first and second horizontal rows of a plurality of slots pass through the backplane member from the back to the front major surfaces. A retainer strap is fitted through a pair of slots in each row and is closable to form a circuit, which may be sized to fit around a post, branch or trunk abutting the back major surface of the backplane. A support is pivotally attached to the front major surface and is positionable to provide a ledge.

Abstract: Systems for delivering a bifurcated stent to a bifurcation site comprise catheters and/or bifurcated stents delivered therefrom.

Abstract: An Electrically Erasable Programmable Read Only Memory (EEPROM) cell uses a single standard NMOS (or PMOS) transistor with its gate connected to a Metal-Insulator-Metal, or Poly-Insulator-Poly capacitor such that a floating gate is formed. The floating gate is programmed and erased via Fowler-Nordheim tunneling.

Abstract: Systems for delivering a bifurcated stent to a bifurcation site comprise catheters and/or bifurcated stents delivered therefrom.

Abstract: A bifurcated stent comprises a first stent section and a second stent section. Each stent section is expandable from a predeployed state to a deployed state independently from one another. The second stent section having an end engaged to a receiving region of the first stent section. In the deployed state the first stent section defines a primary flow path and the second stent section defines a secondary flow path in fluid communication with the first flow path. At least a portion of one or both the first stent section and second stent section is constructed from a wire member.

Abstract: A discrete multi-tone, asymmetrical transceiver and method wherein a modem at a central office transmits information to a modem at a remote terminal on a down-stream signal and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal. The up-stream signal comprising data carried by a lower portion of a predetermined band of frequencies and the down-stream signal comprising data carried by an upper portion of the predetermined band of frequencies. The system includes an interpolator, at the remote terminal, for adding interpolated data into a stream of data distributed by the remote terminal modem among the lower portion of the predetermined band of frequencies for transmission in the up-stream signal. An ADC is provided at the modem of the central office, for converting the down-stream signal into digital samples at a sampling rate greater than the frequency of the highest frequency in the down-stream signal.

Abstract: Delta sigma modulators for accepting input signals having amplitudes up to -1 dB of full-scale and a center frequency (F.sub.S) in the range ?F.sub.S /90, 44F 90!, and which are not prone to internal overflow, require few circuit parameters, and yield a signal transfer function with the inherent property that the modulator magnitude response is close to unity gain in the frequency region of interest include, in one embodiment, a pair of cascaded integrators, a unit delay element coupled to the output of the second integrator, an analog-to-digital (A/D) converter, and a one-bit digital-to-analog (D/A) converter controlled by output signals from the A/D converter. A first differential summing junction coupled to the output of the D/A converter is responsive to delta sigma modulator input signals. A second differential summing junction, coupled to the output of the first differential summing junction, is also coupled to receive a feedback signal from the second integrator.

Abstract: A delta sigma modulator that has a low power dissipation without sacrificing modulator resolution includes, in one embodiment, a current mode digital to analog converter (DAC) in shunt with a conventional op amp in the first stage of the delta sigma modulator. By adding the current mode DAC in shunt with the first (or only) stage op amp of the delta sigma modulator, the slewing current needed during transients is provided by the combination of the op amp and DAC output signals. Since the DAC provides the slewing current required for the output signal change, the op amp need not apply the slewing current and therefore need only operate at low quiescent power.

Abstract: A delta-sigma modulator includes, in one embodiment, cascaded unit-delay integrators, the number of which is selected depending upon the order desired. The modulator further includes an n-bit (or multi-bit) A/D converter coupled to the output of the last cascaded integrator, and an n-bit (or multi-bit) D/A converter coupled to the output of the A/D converter. A truncator also is coupled to the output of the A/D converter. Truncation error correction is performed digitally by a truncation corrector. A one-bit D/A converter provides feedback from the output of the truncator to differential summing junctions interposed at the input of each unit-delay integrator. The multi-bit D/A converter output signal is fed back to differential summing junctions at the input of the third order and higher unit-delay integrators.

Abstract: A delta sigma modulator which enables each cascaded integrator to settle independently within a full clock period and uses binomial coefficients in the feedback paths to obtain the required sinusoidal shaping of quantizer error, achieves an increase in both the sampling rate and the order to improve resolution. Using a multi-bit quantizer also improves modulator resolution. In one embodiment, the modulator includes a plurality of cascaded unit-delay integrators and utilizes binomial coefficient scaling in the feedback loop. A multi-bit analog-to-digital converter is coupled to receive the output signal of the cascaded unit-delay integrators. The feedback loop includes a multi-bit digital-to-analog converter coupled to the output of the multi-bit analog-to-digital converter. The output of the digital-to-analog converter is coupled to the inputs of at least the first and second differential summing junctions.

Abstract: A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time. The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison. The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO). The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator.

Abstract: An improved ground cover. The ground cover is comprised of mulch and a binder. The mulch is molded into the shape desired and held together by the binder. The mulch is comprised of a plurality of small pieces. The binder surrounds the mulch and holds the mulch together. The mulch bound together is both gas and water permeable. Also, the bound mulch is biodegradable and harmless to soil and plants. The mulch may contain leachable plant nutriments. The mulch is opaque so as to retard weed growth and able to retain water.

Abstract: A phase-locked loop having automatic internal phase offset calibration includes a voltage-controlled oscillator circuit for generating a recovered data signal in response to an error signal. A phase detector determines the phase difference between the recovered data signal and a reference data signal. The phase-locked loop further includes a charge pump circuit, coupled to the phase detector, for generating an error signal in response to the detected phase difference. The charge pump circuit includes first and second pump generators for respectively providing first and second sets of pump signals, with the pump generators being interconnected to facilitate generation of the error signal. The phase-locked loop is designed to alternate between operation in phase correction and phase calibration cycles. In each phase correction cycle an error signal is synthesized as described above on the basis of the most recent phase comparison.

Abstract: A phase detector and charge pump combination is disclosed for use in a digital phase locked loop system. The phase detector includes a reset circuit that responds to the charge pump condition where it is simultaneously sourcing and sinking current. The pump up and down circuits are fast acting and balanced so that minimum conduction is employed for the phase lock condition.

Abstract: A portable truck cap comprising a plurality of frame members, which are detachably connected to each other to form a frame, the frame has a top portion and a base portion, the top portion is resilient, the base portion is detachably connectable to a truck. A flexible cover is disposed over the frame, and detachably connected to said base portion of the frame. The cover is tensioned by the top portion of the frame to maintain the cover in a predetermined configuration.