Abstract: A computer memory control capable of controlling a virtual memory system and optimized for handling multi-tasking or multi-processing systems is disclosed. In operation, each task or process is assigned a unique process number. The memory control circuitry which translates a virtual address produced by the system processor into a physical address suitable for memory access includes a unique translation buffer store each entry of which comprises a physical address, the usual tag bits and the process number of the process utilizing that address. During an address translation, buffer store entries are indexed using the virtual address used by the processor. In addition to the usual tag bit comparison to verify data validity, a comparison is made between the process number of the process presently running and the process number stored at the indexed buffer entry. The translation is considered successful only if both the tag bits and the process numbers match.

Abstract: A data processing system including a plurality of data units and a common bus. The data unit includes apparatus for issuing instructions including a LOCK instruction and an UNLOCK instruction. Each data unit includes apparatus responsive to the instructions such that, if the first data unit issues a LOCK instruction, the data unit other than the first data unit, are prevented from transferring information over the common bus with a LOCK instruction until an UNLOCK instruction is issued by any data unit.

Abstract: A data processing system in which a unit needing to be serviced by a processor first requests an interrupt and, after the interrupt is granted by the processor, requests access to a system bus to transfer interrupt information as it normally would transfer other information. The interrupting unit must wait for other units having higher priority to transfer information, usually memory information over the bus, before it can access the bus to transfer its interrupting information. This permits transfers of information having higher priority to occur before the transfer of the interrupt information is transferred.