Abstract: An instruction is received by a processing pipeline of a computer processor. The instruction is a constant-type of instruction and has an associated constant value. A constant register file is assigned to the instruction. The constant value is written to the constant register file without sending the instruction to execution units (e.g., arithmetic logic units) in the processor pipeline.

Abstract: A heat exchanger includes an inlet for receiving bulk solids, a plurality of heat transfer plate assemblies, a plurality of spacers disposed between adjacent heat transfer plate assemblies, and supports for supporting the heat transfer plate assemblies. The heat transfer plate assemblies include a first plate having a first pair of holes extending therethrough, the first plate having channels extending along a surface thereof, for the flow of fluid through the channels, and a second plate bonded to the first plate to enclose the channels, the second plate including a second pair of holes generally aligned with the first pair of holes to form through holes to facilitate flow of the fluid through the through holes and the channels.

Abstract: The present disclosure is directed to compounds that may selectively inhibit Death Associated Protein Kinases (DAPKs) as well as PIM kinases. The compounds can be used in methods of treating various disorders, including cancers.

Abstract: A system for preparing a bone for receiving an implant is described. The system includes a cutting tool and a cutting guide. The cutting tool includes a cut guard configured to sheath at least a portion of a cutting surface of the cutting tool, and an engagement portion. The cutting guide includes a baseplate configured to be positioned onto the bone and a cut guide portion removably attached to the baseplate. The cut guide portion includes a cutting channel, the cutting channel being sized and shaped to receive the engagement portion of the cut guard and guide the cutting tool to cut a receiving channel into the bone, wherein the receiving channel includes a depth profile matching an implant to be inserted into the receiving channel.

Abstract: A data structure (e.g., a table) stores a listing of prefetches. Each entry in the data structure includes a respective virtual address and a respective prefetch stride for a corresponding prefetch. If the virtual address of a memory request (e.g., a request to load or fetch data) matches an entry in the data structure, then the value of a counter associated with that entry is incremented. If the value of the counter satisfies a threshold, then the lookahead amount associated with the memory request is increased.

Abstract: A system and corresponding method map instructions in an out-of-order (OoO) processor. The system comprises a mapper, integer snapshot circuitry, and floating-point (FP) snapshot circuitry. The mapper maps instructions by mapping integer and FP architectural registers (ARs) of the instructions to integer and FP physical registers of the OoO processor, respectively. The mapper records, via at least one present FP indicator, presence of FP ARs used as destinations in the instructions. The mapper copies, periodically, the integer mapper state to the integer snapshot circuitry and copies, intermittently, based on the at least one FP present indicator, the FP mapper state to the FP snapshot circuitry. Copies of the integer and FP mapper state in the integer and FP snapshot circuitry, respectively, improve performance for instruction unwinding caused, for example, by an exception, branch/jump mispredict, etc. By copying the FP mapper state, intermittently, power efficiency of the OoO processor is improved.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: A first memory request including a first virtual address is received. An entry in memory is accessed. The entry is selected using information associated with the first memory request, and includes at least a portion of a second virtual address (first data) and at least a portion of a third virtual address (second data). The difference between the first data and the second data is compared with differences between a corresponding portion of the first virtual address and the first data and the second data respectively. When a result of the comparison is true, then a fourth virtual address is determined by adding the difference between the first data and the second data to the first virtual address, and then data at the fourth virtual address is prefetched into the cache.

Abstract: A merge unit configured to perform merge and permutation micro-operations by multiplexing data bytes of the inputs to simultaneously produce multiple data bytes of a merge and permutation result. Particularly, the merge unit includes a bank of MUXs arranged in parallel, each corresponding to one or more different data bytes in the merge result. When the merge unit is provided with a set of inputs, each MUX multiplexes the data bytes of the set of inputs (e.g., all the data bytes of the set of inputs) to selectively output a data byte to a particular location of the destination register storing the merge result. The selection by each MUX is individually controlled by a set of merge control words which identify a data byte location in an input and identify an input from the set of inputs.

Abstract: An ALU is capable of generating a multiply accumulation by compressing like-magnitude partial products. Given N pairs of multiplier and multiplicand, Booth encoding is used to encode the multipliers into M digits, and M partial products are produced for each pair of with each partial product in a smaller precision than a final product. The partial products resulting from the same encoded multiplier digit position, are summed across all the multiplies to produce a summed partial product. In this manner, the partial product summation operations can be advantageously performed in the smaller precision. The M summed partial products are then summed together with an aggregated fixup vector for sign extension. If the N multipliers equal to a constant, a preliminary fixup vector can be generated based on a predetermined value with adjustment on particular bits, where the predetermined value is determined by the signs of the encoded multiplier digits.

Abstract: The present disclosure is directed to compounds that may selectively inhibit Death Associated Protein Kinases (DAPKs) as well as PIM kinases. The compounds can be used in methods of treating various disorders, including cancers.

Abstract: A tantala ring resonator includes a tantala ring resonator formed by ion-beam sputtering of tantalum pentoxide and exhibiting an optical quality factor in excess of 3×106, and a substrate to which the tantala ring resonator is attached. A method for fabricating nonlinear photonic devices includes depositing tantalum pentoxide with ion-beam sputtering to form a tantala layer onto a substrate, annealing the tantala layer, and etching the tantala layer to form a photonic device.

Abstract: The field of the invention relates to bicycle systems, especially to bicycle systems adapted for use with smartphones, to smartphones configured for use with bicycle systems, and to methods and to computer software for use with such bicycle systems or smartphones, and to servers configured to communicate with such bicycle systems or smartphones. According to a first aspect of the invention, there is provided a bicycle system including a bicycle, the bicycle system including a processor integral to the bicycle, the bicycle system further including a battery integral to the bicycle, wherein the processor is powerable by the battery, the bicycle system including a smartphone holder configurable to receive a smartphone and to connect the smartphone to the processor, wherein in use the smartphone holder is attachable to, and detachable from, the smartphone.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Abstract: The invention relates to a method (100) for estimating a cylinder pressure (CP) in an internal combustion engine arrangement (10), the method comprising the steps of: initiating (110) an opening of a valve by an actuator during an expansion stroke; monitoring (120) the valve to determine a point in time (Tp) when the valve opens; determining (130) a differential pressure (DP) between the combustion cylinder and a position in a fluid medium exhaust passage (29, 39, 60) downstream said valve at the point in time (Tp); receiving (140) data being indicative of a pressure (EP) in the fluid medium passage at the point in time (Tp); and determining (150) the cylinder pressure (CP) at the point in time (Tp) based on the determined differential pressure (DP) and the data indicative of the pressure in said fluid medium passage.

Abstract: A pressure relief assembly includes a housing defining an air passage chamber having at least one opening, and a membrane flap secured within the air passage chamber. The membrane flap is configured to move into an open position to expose the opening(s) to relieve air pressure. A plurality of flap-retaining clips securely couple the membrane flap to the housing. Each of the plurality of the flap-retaining clips includes a main body. A housing-connecting tab extends from a first end of the main body. The housing-connecting tab is retained within a retaining channel formed in the housing. Opposed flap-retention wings laterally extend from opposite sides of the main body. A portion of the membrane flap is trapped between the opposed flap-retention wings and the housing to securely couple the membrane flap to the housing.

Abstract: The present invention relates to a method for controlling an internal combustion engine arrangement (100). The internal combustion engine arrangement (100) comprises a combustion cylinder (102) and an inlet valve (106) arranged to be positioned in a closed position at a distance before a piston (104) reaches a bottom dead center during normal operation. The inlet valve is further controllable to be arranged in the open position until the piston reaches the bottom dead center if a required volumetric efficiency of the combustion cylinder is higher than a volumetric efficiency during normal operation.

Abstract: The invention relates to a system (100) for operating a valve of an internal combustion engine (10), said system comprising a primary fluid circuit (60) configured to define a fluid passageway for circulating a compressible fluid medium there through being operatively connectable to an actuator (92) of an actuated flow control valve (90, 95) of said internal combustion engine, thereby capable of delivering a valve opening force.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. Advantageously, this allows a user, who is interfacing with the hardware processor through software, to provide data to the processor agnostic to the size of the registers and datapath bit-width of the processor.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.