Abstract: Disclosed are various embodiments for network monitoring. A processor circuit having a processor and a memory is employed. A listing of components of a network is stored in the memory, the listing including a plurality of endpoints and a plurality of nodes. One of the endpoints includes a processor circuit. A monitoring application is stored in the memory and executable by the processor circuit. The monitoring application is configured to maintain in the memory an indication of an operational status of each of the nodes derived from a plurality of status requests transmitted between respective pairs of the endpoints.

Abstract: Disclosed are various embodiments for network monitoring. A processor circuit having a processor and a memory is employed. A listing of components of a network is stored in the memory, the listing including a plurality of endpoints and a plurality of nodes. One of the endpoints includes a processor circuit. A monitoring application is stored in the memory and executable by the processor circuit. The monitoring application is configured to maintain in the memory an indication of an operational status of each of the nodes derived from a plurality of status requests transmitted between respective pairs of the endpoints.

Abstract: Disclosed are various embodiments for network monitoring. A processor circuit having a processor and a memory is employed. A listing of components of a network is stored in the memory, the listing including a plurality of endpoints and a plurality of nodes. One of the endpoints includes the processor circuit. A monitoring application is stored in the memory and executable by the processor. The monitoring application is configured to maintain in the memory an indication of an operational status of each of the nodes derived from a plurality of status requests transmitted between respective pairs of the endpoints.

Abstract: Disclosed are various embodiments for network monitoring. A processor circuit having a processor and a memory is employed. A listing of components of a network is stored in the memory, the listing including a plurality of endpoints and a plurality of nodes. One of the endpoints includes the processor circuit. A monitoring application is stored in the memory and executable by the processor. The monitoring application is configured to maintain in the memory an indication of an operational status of each of the nodes derived from a plurality of status requests transmitted between respective pairs of the endpoints.

Abstract: Disclosed are various embodiments for using contributor-provided attributes in conjunction with an electronic item catalog. A request is received from a catalog user to obtain information an item in a catalog of items. Responsive to the request, the catalog is queried to obtain a plurality of attributes associated with the item. The attributes include at least one operator-controlled attribute and at least one contributor-provided attribute. A page is generated for display to the catalog user. The page includes the at least one operator-controlled attribute and at least one contributor-provided attribute.

Abstract: One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line with a predetermined transmission signal time delay. The output is adapted to produce an inverted signal with respect to a signal received at the input. The transmission line has a first end connected to the output and a second end connected to the input. Other aspects and embodiments are provided herein.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a CMOS amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: An apparatus which provides the ability to charge or power multiple devices from multiple different power sources, and to communicate electronic data to and from one of the devices. The apparatus utilizes simple construction, requiring no active electronics, thereby reducing the cost of production and the reliability of the device. The apparatus employs a single USB connection cable with connectors on both ends and a second power-only cable and connector which is connected to the power wires of the USB cable and thereby is able to power a second portable device from a single USB port. USB master provide sufficient power for two average portable devices without additional circuitry. Moreover, restricting the data path to only one device also eliminates the need for USB hub circuitry.

Abstract: One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line with a predetermined transmission signal time delay. The output is adapted to produce an inverted signal with respect to a signal received at the input. The transmission line has a first end connected to the output and a second end connected to the input. Other aspects and embodiments are provided herein.

Abstract: The present invention comprises switched capacitor amplifiers including positive feedback, semiconductor devices, wafers and systems incorporating same and methods for amplifying signals using positive feedback, while maintaining a stable gain and producing an improved signal-to-noise ratio. One embodiment includes a switched capacitor amplifier comprising a Complementary Metal Oxide Semiconductor (CMOS) amplifier, a feed-in switched capacitor, and a feedback switched capacitor. The feed-in switched capacitor operably couples an input signal to the non-inverting input of the CMOS amplifier. Similarly, the feedback switched capacitor operably couples the amplifier output to the non-inverting input to create a positive feedback loop. A capacitance of the feedback switched capacitor relative to a capacitance of the feed-in switched capacitor comprises a feedback proportion.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A technique for reducing 1/f noise in an imager, in which the source follower transistor in a pixel circuit is turned off prior to a correlated double sampling (CDS) operation, thereby reducing 1/f noise in the source follower transistor for up to 100 ms. The source follower transistor is then reactivated and a CDS operation and readout is performed normally. This technique substantially reduces the contributions of 1/f noise. The invention also provides a reduction of 1/f noise in an analog amplifier circuit which may process pixel output signals, or more generally, other analog signals, whereby the analog amplifier is turned off during an amplifier reset operation prior to signal amplification. The analog amplifier circuit may be a differential amplifier or a switched capacitor analog amplifier circuit.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

Abstract: The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor coupled to a differential input of the CMOS differential amplifier is used to inject current into the differential input, such that the net current flow through the gate-to-drain capacitance of a MOS input transistor approaches zero. Thus, the Miller effect with respect to that MOS input transistor is substantially reduced or eliminated, resulting in increased frequency and transient responses for the CMOS differential amplifier. In one embodiment, the CMOS differential amplifier is a CMOS current mirror differential amplifier.

Abstract: A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a bit line of a memory circuit when the sense amplifier is reset and a signal voltage on the same bit line when a signal representing a data bit is present in the bit line. The differential amplifier amplifies the difference between the signal voltage and the reference voltage.

Abstract: Methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract: An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture across all of the pins of an integrated circuit device. The printed circuit board includes an array of substantially similar test contacts numbering greater than the pins of the integrated circuit device. The array of test contacts includes an active portion configured for electrically coupling with the corresponding pins on the integrated circuit device and an inactive portion adjacent to the active portion and electrically coupled to a reference signal on the printed circuit board.