Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Abstract: Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Abstract: An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise vertically-alternating tiers comprising control gate material of individual charge storage field effect transistors vertically alternating with insulating material. An upper stack channel pillar extends through multiple of the vertically-alternating tiers in the upper stack and a lower stack channel pillar extends through multiple of the vertically-alternating tiers in the lower stack. Tunnel insulator, charge storage material, and control gate blocking insulator is laterally between the respective upper and lower stack channel pillars and the control gate material. A conductive interconnect comprising conductively-doped semiconductor material is elevationally between and electrically couples the upper and lower stack channel pillars together. The conductively-doped semiconductor material comprises a first conductivity-producing dopant.

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.

Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Abstract: Integrated circuitry comprises an array circuitry region comprising a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

Abstract: Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.