Patents by Inventor David A. Dunn

David A. Dunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data structure for enforcing consistent per-physical page cacheability attributes
    Patent number: 8607025
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: December 10, 2013
    Inventors: Alexander C. Klaiber, David Dunn
  • INTEGRATED TESTING DEVICE
    Publication number: 20130323123
    Abstract: An integrated testing device and method are disclosed. The device includes an integral reservoir for a test fluid, and an actuator, so that the test fluid can be dispensed to facilitate the test.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 5, 2013
    Applicant: ATOMO DIAGNOSTICS PTY LIMITED
    Inventors: John Michael KELLY, Eric SIU, Alison Ruth NORCOTT, Christopher David DUNN, Ian Frederick JOHNSON, Ernesto Monis HUESO, Richard SOKOLOV
  • INSTRUCTION-OPTIMIZING PROCESSOR WITH BRANCH-COUNT TABLE IN HARDWARE
    Publication number: 20130311752
    Abstract: A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Rupert Brauch, Madhu Swarna, Ross Segelken, David Dunn, Ben Hertzberg
  • TRANSLATION ADDRESS CACHE FOR A MICROPROCESSOR
    Publication number: 20130246709
    Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Ross Segelken, Alex Klaiber, Nathan Tuck, David Dunn
  • History based pipelined branch prediction
    Patent number: 8473727
    Abstract: Systems and methods for history based pipelined branch prediction. In one example, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: June 25, 2013
    Inventors: David A. Dunn, John P. Banning
  • DIAGNOSTIC SYSTEM
    Publication number: 20130131479
    Abstract: A composite diagnostic system comprising a support member having a membrane penetration element; a bodily fluid collection point positioned for collection of a bodily fluid released by application of the membrane penetration element to a user's body; a test material positioned in the support member such that in use the bodily fluid is brought into contact with the test material.
    Type: Application
    Filed: March 18, 2011
    Publication date: May 23, 2013
    Inventors: John Michael Kelly, Eric Siu, Alison Ruth Norcott, Christopher David Dunn, Ian Frederick Johnson, Ernesto Monis Hueso, Richard Sokolov
  • Two piece corner framing element for swimming pool extrusions with pool-liner anchor channels
    Patent number: 8291528
    Abstract: An two-piece, corner framing element is described for connecting two longitudinal swimming pool extrusions having longitudinal pool-liner channels that utilizes the conventional upward projecting liner-anchoring land along a bottom front edge of the pool-liner channels for angularly orienting and securing the longitudinal extrusions together in the field framing a pool corner wall during construction of a swimming pool.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 23, 2012
    Inventors: David Dunn, Harry J. Last
  • SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE
    Publication number: 20120254584
    Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Inventors: Guillermo Rozas, Alexander Klaiber, H. Peter Anvin, David Dunn
  • System and method for identifying TLB entries associated with a physical address of a specified range
    Patent number: 8239656
    Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 7, 2012
    Inventors: Guillermo Rozas, Alexander Klaiber, H. Peter Anvin, David Dunn
  • Two piece corner framing element for swimming pool extrusions with pool-liner anchor channels
    Patent number: 8205319
    Abstract: An two-piece, corner framing element is described for connecting two longitudinal swimming pool extrusions having longitudinal pool-liner channels that utilizes the conventional upward projecting liner-anchoring land along a bottom front edge of the pool-liner channels for angularly orienting and securing the longitudinal extrusions together in the field for framing a corner structure for pool walls as a pool is being constructed.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 26, 2012
    Inventors: David Dunn, Harry J. Last
  • DEVICE FOR DISPENSING AN ADDITIVE IN AN APPLIANCE
    Publication number: 20120144878
    Abstract: Embodiments of an appliance are described that are configured for bulk handling and dispensing of an additive. The appliance includes a dispensing device that has in one example a bulk compartment and a dispense compartment. The dispensing device also includes a flow control device such as a valve that controls gravity-flow communication of the additive between the bulk compartment and the dispense compartment. In one embodiment, a fluid conduit carries a washing fluid such as water to the dispense compartment, thereby flushing the additive from the dispense compartment and into a wash tub of the appliance.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Inventors: Alaknanda Acharya, David Dunn, Mohan Ponnaganti
  • DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES
    Publication number: 20120131307
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Inventors: Alexander C. Klaiber, David Dunn
  • SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE
    Publication number: 20120072697
    Abstract: A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.
    Type: Application
    Filed: March 22, 2011
    Publication date: March 22, 2012
    Inventors: Guillermo Rozas, Alexander Klaiber, H. Peter Anvin, David Dunn
  • HISTORY BASED PIPELINED BRANCH PREDICTION
    Publication number: 20120072708
    Abstract: Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.
    Type: Application
    Filed: August 6, 2010
    Publication date: March 22, 2012
    Inventors: David A. Dunn, John P. Banning
  • Data structure for enforcing consistent per-physical page cacheability attributes
    Patent number: 8117421
    Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: February 14, 2012
    Inventors: Alexander C. Klaiber, David Dunn
  • Explicit control of speculation
    Patent number: 8078853
    Abstract: Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocessor, while speculation normally permitted for certain other operations is suspended. Accordingly, while the fault is dispatched, some speculation is permitted as opposed to suspending all speculation. As such, microcode that makes use of speculation can be written.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: December 13, 2011
    Inventors: H. Peter Anvin, David Dunn
  • CONNECTOR AND MEDICAL DEVICE SYSTEM INCORPORATING SAME
    Publication number: 20110277240
    Abstract: In one aspect, the invention is directed to a connector for connecting a medical device to a support member on a patient support device, such as a stretcher. The connector includes a support member connector that is fixedly connectable to the support member and a device connector for fixedly connecting to the medical device. The device connector is movable relative to the support member connector between a first position wherein the device connector is positioned to hold the medical device adjacent the patient support device and a second position that is inboard of the first position relative to the patient support device.
    Type: Application
    Filed: May 1, 2009
    Publication date: November 17, 2011
    Inventors: Veso Tijanic, Joseph Fisher, Bryan Kowalchuk, Bryan Drew Miller, Kevin Ramkhelawan, Kevin Kowalchuk, Cliff Ansel, David Dunn, Ludwik Fedorko
  • Input/Output Request Packet Handling Techniques by a Device Specific Kernel Mode Driver
    Publication number: 20110216780
    Abstract: The input/output request packet (IRP) handling technique includes determining if a received input/output request packet should receive a given handling. If the input/output request packet should receive the given handling, the input/output request packet is dispatched to a device specific dispatch input/output request packet handler. Otherwise, the input/output request packet is redirected to an operating system dispatch input/output request packet handler.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 8, 2011
    Applicant: NVIDIA CORPORATION
    Inventors: Timothy Zhu, David Dunn, Randy Spurlock, Thomas Spacie
  • Maintaining instruction coherency in a translation-based computer system architecture
    Patent number: 7971002
    Abstract: Methods and systems for maintaining instruction coherency in a translation-based computer system architecture are described. A translation coherence cache memory can be used to store a memory page reference that identifies a memory page. The cache memory also stores a permission bit corresponding to the memory page reference. The permission bit indicates whether the memory page comprises code that has been translated into another form.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 28, 2011
    Inventors: Guillermo Rozas, David Dunn
  • System management and advanced programmable interrupt controller
    Patent number: 7958296
    Abstract: Methods for processing more securely are disclosed. Embodiments provide effective and efficient mechanisms for reducing APIC interference with accesses to SMRAM, where enhanced SMM code implementing these mechanisms effectively reduces APIC attacks and increases the security of proprietary, confidential or otherwise secure data stored in SMRAM.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: June 7, 2011
    Inventor: David A. Dunn