Abstract: A method and apparatus are provided for enabling multiple users to concurrently access a PC-based server in a home local area network using conventional TVs as display devices. A client system includes a TV, conventional input devices, such as a keyboard and a mouse, and a set top box for interfacing the TV to the network. The server maintains a system work area and multiple processes corresponding to user applications. The system work area is partitioned in the server into multiple independent, simultaneously active desktops, one desktop for each of the client systems. Individual processes are mapped to the appropriate desktop. Multiple frame buffers are maintained in the server, such that a different frame buffer is assigned to each client system. Each desktop is rendered within the server and stored in the corresponding frame buffer. The contents of each frame buffer are transmitted over a transmission medium to the set top box of the corresponding client system.

Abstract: A multi-terminal transistor circuit structure is described for TTL applications including current sinking and "pull-down" transistor circuit elements. A transistor pair is coupled with the emitter of the second transistor coupled to the base of the first transistor. The collector and emitter of the first transistor provide first and second terminals and the bases of the transistor pair provide independent third and fourth terminals or current controlled inputs. The new circuit structure is incorporated in a tranistor transistor logic (TTL) output buffer circuit and provides first and second pull-down transistor elements having the emitter of the second transistor coupled to the base of the first pull-down transistor. An independent base drive is coupled to the base of the second pull-down transistor element. The second stage pull-down transistor element introduces full square law enhancement of .beta..sup.

Abstract: A multiple phase-splitter TTL tristate output circuit having a feedback diode coupled between the signal output and the collector of a first phase-splitter transistor to accelerate sinking of current from the output to low potential during transition of binary signals at the output from high to low potential. An independent base drive is coupled to the base of the first phase-splitter transistor independent from any base drive coupled to the other phase-splitter transistor or transistors. Current hogging of the base drive current to the first phase-splitter transistor by the other phase-splitter transistors is thereby prevented. The first phase-splitter transistor which is coupled in the feedback circuit with the accelerating feedback diode to the base of the pulldown transistor element can therefore maintain the high current sinking mode through the pulldown transistor element with gain step-up proportional to .beta..sup.2 when the output is at the high voltage level.

Abstract: An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance.

Abstract: A data latch of the kind having at least two operative modes, a transmitting or transparent mode or condition for transmitting data signals through the latch, and a latching mode or condition for latching and temporary storage by feedback of data signals in the latch. According to the invention there is provided in the data latch a pregate for pregating feedback signals in the latch. The pregate is adapted and coupled to provide positive feedback data signals for reinforcing previously entered data in the latching mode, and gating signals for passing input data in the transmitting mode.

Abstract: A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used.