Abstract: Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

Abstract: Methods, systems, devices, and products for performing well logging in a borehole intersecting an earth formation to obtain and transmit an acoustic reflection image of the formation. Methods include identifying a set of features in the acoustic reflection image substantially fitting a pattern, wherein the set of features corresponds to a portion of at least one reflecting structural interface of the formation; and using a representation of the pattern as the compressed representation of the acoustic reflection image. The features may be amplitude peaks in the acoustic reflection image, and the pattern may be a line segment therein that is obtained from the amplitude peaks. Identifying the set of features may include generating a binary image of the amplitude peaks.

Abstract: Methods, systems, devices, and products for performing well logging in a borehole intersecting an earth formation to obtain and transmit an acoustic reflection image of the formation. Methods include identifying a set of features in the acoustic reflection image substantially fitting a pattern, wherein the set of features corresponds to a portion of at least one reflecting structural interface of the formation; and using a representation of the pattern as the compressed representation of the acoustic reflection image. The features may be amplitude peaks in the acoustic reflection image, and the pattern may be a line segment therein that is obtained from the amplitude peaks. Identifying the set of features may include generating a binary image of the amplitude peaks.

Abstract: A differential feedback equalizer is described. A differential feedback equalizer comprises a summer circuit configured to receive a differential input signal and a summer tap circuit output and to generate a summer circuit differential output; a first latch configured to receive the summer circuit differential output from the summer circuit and to generate a first differential latch output comprising a first state of the differential feedback equalizer; and a feedback circuit having a NAND gate coupled to an output of the first latch and configured to generate a differential tap feedback signal; wherein the feedback circuit comprises a NAND gate buffer that maintains the differential tap feedback signal at a predetermined voltage during a reset phase of the first latch. A method of implementing a differential feedback equalizer is also described.

Abstract: A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the C2 clocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a C2 clock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the C2 clocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation.

Abstract: A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the C2 clocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a C2 clock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the C2 clocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation.

Abstract: A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Abstract: A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Abstract: Magneto-Resistive (MR) head read/write channel (400) provides timer (421), detector (433) and amplifier (432) to reduce the amount of time required to transition from read mode to write mode. Controller (410) issues the write command (WGATE) to signal a pending mode change from read to write mode. While read/write channel (400) remains in read mode, timer (421) begins a configurable countdown sequence, which allows Arm Electronics (430), except for a final output stage of amplifier (432), to power up in preparation for write mode. Once timer (421) has reached terminal count, signal (CHWGATE) is de-asserted, which causes write channel (422) to warm up. After warm up, write channel (422) writes serial data (WRITE DATA) to detector (433). Still in read mode, detector (433) detects the presence of WRITE DATA from write channel (422) and asserts signal (AEWGATE).

Abstract: Magneto-Resistive (MR) head read/write channel (400) provides timer (421), detector (433) and amplifier (432) to reduce the amount of time required to transition from read mode to write mode. Controller (410) issues the write command (WGATE) to signal a pending mode change from read to write mode. While read/write channel (400) remains in read mode, timer (421) begins a configurable countdown sequence, which allows Arm Electronics (430), except for a final output stage of amplifier (432), to power up in preparation for write mode. Once timer (421) has reached terminal count, signal (CHWGATE) is de-asserted, which causes write channel (422) to warm up. After warm up, write channel (422) writes serial data (WRITE DATA) to detector (433). Still in read mode, detector (433) detects the presence of WRITE DATA from write channel (422) and asserts signal (AEWGATE).

Abstract: A method and apparatus for improving baseline recovery of an MR head using a programmable AC coupling pole. The location of the pole may be adjusted to achieve the fastest recovery from a baseline shift without degrading the normal channel performance. Further, the pole may be moved during the data recovery procedure to recover from a data read error. The programmable AC coupling pole includes a circuit path carrying digital data signals read from a recording media by a magnetic head, an amplifier coupled to the circuit path for amplifying the digital data signals, and a recovery time setting device having an programmable recovery time constant associated therewith. Once a data read error has been detected by the system, the recovery time constant may be adjusted to set a recovery time for the amplifier to provide readable data signals.

Abstract: A method and apparatus for improving baseline recovery of an MR head using a programmable AC coupling pole. The location of the pole may be adjusted to achieve the fastest recovery from a baseline shift without degrading the normal channel performance. Further, the pole may be moved during the data recovery procedure to recover from a data read error. The programmable AC coupling pole includes a circuit path carrying digital data signals read from a recording media by a magnetic head, an amplifier coupled to the circuit path for amplifying the digital data signals, and a recovery time setting means having an programmable recovery time constant associated therewith. Once a data read error has been detected by the system, the recovery time constant may be adjusted to set a recovery time for the amplifier to provide readable data signals.

Abstract: The present invention concerns an apparatus, method, and article of manufacture that satisfies the need for verifying the identity of a designated head in a gang servo head environment by querying a control parameter unit. In one embodiment, the invention may be implemented to provide a method to increase head select robustness for group head systems controlled by drive electronics. The method is practiced when a request is made for a designated head to perform a read or write operation. The request is received by a control parameter unit included in an arm electronics unit. The control parameter unit is then queried to verify the identity of the arm electronics unit selected. The identity of the designated head is then received. A parity check of the control data is performed and, assuming no errors, an actuating arm containing the designated head is positioned. The selected arm electronics unit is loaded with read or write data copied from a host system and transferred to or from the storage device.

Abstract: Logic for detecting the reliability of an address in Pennington code (PCODE). The address is parsed into two separate halves. The first half corresponds to the front portion of the PCODE address and the second half corresponds to the back portion of the same. The two halves are compared to determine the reliability of the address. If the address is not reliable, a head position estimation is used to position the head over the described track. If the address is reliable, the PCODE is combined with a position error signal to position the head.

Abstract: A servo signal demodulator for a banded data disk drive system includes a single data sampling clock for both the data channel sampling and the servo data sampling. The demodulator includes an analog-to-digital converter that receives a readback signal from a read/write head of the disk drive system and generates samples of the readback signal in accordance with a repeating sampling clock signal whose frequency changes as a function of a data band of the disk drive over which the read/write head is positioned, an adder that sums the readback signal samples from the analog-to-digital converter to thereby produce an integrated readback signal value, and a servo signal decoder circuit that latches the adder sum to a register after the adder has summed a sufficient number of readback signal samples to comprise a servo burst, in accordance with a data channel sampling clock signal, and provides demodulated signal information to a servo controller.

Abstract: A fully differential operational amplifier having unity gain is provided. The amplifier includes a differential input stage having two pairs of differential inputs. One pair receives the input signal. The other pair is connected internally to receive differential mode feedback from the output stage. The two pairs of differential inputs are combined with a common mode feedback signal and cascoded to the output. The amplifier incorporates automatic internal noise cancellation due to its differential mode feedback, and may be constructed in MOS logic, or in BiCMOS for high frequency operation. Applications include buffering for filters in circuitry requiring high speed and noise cancellation, such as data channels and servo channels in data recording devices.