Patents by Inventor David A. Gilda

David A. Gilda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6115795
    Abstract: A coherency controller for configurable caches. A base microprocessor design accommodates system configurations both with and without L2 cache tag and data arrays installed. Second level cache control logic exists within the microprocessor chip, and when the external second level cache tag and data arrays are removed their inputs to the microprocessor are tied to an inactive state. A configuration switch is set in the second level cache controller that causes snoop requests from a system bus to get reflected onto a first level cache snooping path. The first level cache status is then fed back to the second level cache controller, in a manner consistent with the timing required for support of a second level cache search, and fed into the second level cache status signal generation logic, effectively making the second level cache controller believe that the second level cache still exists for snooping.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Glenn David Gilda, Steven Lee Gregor
  • Patent number: 6065101
    Abstract: A cache system is provided for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A two level cache subsystem including an L1 cache and an L2 cache is provided. A cache directory is accessed for a second snoop request while a directory access from a first snoop request is being evaluated. During a REQUEST stage, a directory access snoop to the directory of the L1 cache is requested; and responsive thereto, during a SNOOP stage, the directory is accessed; during an ACCESS stage, the cache arrays are accessed while processing results from the SNOOP stage. If multiple data transfers are required out of the L1 cache, a pipeline hold is issued to the REQUEST and SNOOP stages, and the ACCESS stage is repeated. During a FLUSH stage, cache data read from the L1 cache during the ACCESS stage is sent to the L2 cache.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: May 16, 2000
    Assignee: International Business Machines Corporation
    Inventor: Glenn David Gilda
  • Patent number: 4333588
    Abstract: An ice dispenser assembly including an ice piece storage receptacle having an open top and including means for dispensing ice pieces contained therein. A stationary track member is provided on each side of the ice piece storage receptacle and each track member has a rearward horizontal portion, a forward downwardly curved portion, and a forward upwardly curved portion. Two pairs of spaced guide elements, each pair including a forward guide element and a rearward guide element are secured to the receptacle on each side thereof and slidable in each of the stationary track members to move the ice piece storage receptacle from a first position to a second position.
    Type: Grant
    Filed: August 8, 1980
    Date of Patent: June 8, 1982
    Assignee: General Electric Company
    Inventors: Raymond M. Schreck, Bill G. Brown, David A. Gilda