Abstract: The present invention relates to chemical processes for the manufacture of certain quinazoline derivatives, or pharmaceutically acceptable salts thereof. The invention also relates to processes for the manufacture of certain intermediates useful in the manufacture of the quinazoline derivatives and to processes for the manufacture of the quinazoline derivatives utilising said intermediates. In particular, the present invention relates to chemical processes and intermediates useful in the manufacture of the compound 4-(4-bromo-2-fluoroanilino)-6-methoxy-7-(1-methylpiperidin-4-ylmethoxy)quinazoline.

Abstract: The present invention relates to chemical processes for the manufacture of certain quinazoline derivatives, or pharmaceutically acceptable salts thereof. The invention also relates to processes for the manufacture of certain intermediates useful in the manufacture of the quinazoline derivatives and to processes for the manufacture of the quinazoline derivatives utilising said intermediates. In particular, the present invention relates to chemical processes and intermediates useful in the manufacture of the compound 4-(4-bromo-2-fluoroanilino)-6-methoxy-7-(1-methylpiperidin-4-ylmethoxy)quinazoline.

Abstract: A fishing rod is strengthened with a metal reinforcement chosen from a metal coating deposited on a formed rod section and a metal wire in a substantially non-crossing arrangement, or a combination of these. In a base section of the rod, wire is wrapped in a single spiral direction so that the wire substantially does not cross itself. In a tip section, wire is arranged to follow the elongated section in a long spiral or substantially linear path, again not substantially crossing itself. The absence of crossing wires allows improved sensitivity and casting accuracy in the rod and eliminates the potential for crossing wires to separate when the rod flexes.

Abstract: The invention is a control system using microprocessors which communicate through a Local Area Network (private LAN) to control operation of both processors and input and output subsystems (IO system) of a multiprocessor computer system. The processors each have memory associated therewith, and each processor has an IO system comprising a plurality of busses such as PCI busses, associated therewith. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or delivered to an IO system associated with the destination processor, etc.

Abstract: The bit rate at which a digital wireless communications system communicates data in scattering environments may be significantly increased by using multiple antennas at both the transmitter and receiver and by decomposing the channel into m subchannels. In the same frequency band, m one dimensional signals are transmitted into a scattering environment which makes these transmitted signals appear spatially independent at the receiver antenna array. The high bit rate is enabled by special receiver processing to maximize the minimum signal-to-noise ratio of the receiver detection process.

Abstract: The processors of a multiprocessor system are managed, or controlled, by a microprocessors referred to as MBM microprocessors, and the input/output units of the multiprocessor system are managed or controlled by microprocessors contained in PBM units. The MBM units and PBM units communicate with each other through a private local area network. The processors may be arranged into partitions by software, where the processors of a partition may exchange messages with each other, but not with other processors of the multiprocessor system. A virtual time of year clock synchronizes the microprocessors of the MBM and PBM units within a partition to form a “base time”. In the event that the operating system of a partition changes the time within that partition, a “delta time” is computed such that the base time plus the delta time gives the set time. The delta time is stored in a database which is replicated within all MBM and PBM microprocessors.

Abstract: A control system using microprocessors for communicating through a LAN to control operation of processors and input and output subsystems (IO system) of a multi-processor computer system. Each processor includes memory, and an IO system comprising a plurality of busses. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or an IO system associated with the destination processor, etc. The processors and IO system are mounted in a rack, and an IO system is associated with each processor. A rack may be hot swapped. In hot swapping, the microprocessor control system computes new routing tables for messages through the new cabling arrangement. Microprocessors, IO devices, and processor boards may be hot swapped.

Abstract: An automated backplane cable connection system (and method) for manually connecting a cluster of processor modules to other modules or I/O boxes uses a programmed server management control console which identifies connection terminals provided on the processors/I/O boxes and controls LEDs which are associated with the connection terminals, on a one to one basis. The programmed server management console uses diagnostic circuitry and causes LEDs corresponding to connection terminals engaged by a newly made cable connection to initially light up, and enables them to turn off if the newly made cable connection is proper as verified by the diagnostic circuitry. The cluster of processor modules may be connected to a plurality of I/O boxes through an Ethernet LAN. The processor modules or I/O boxes may have sufficient nonvolatile memory to remember backplane cable connections which have already been made according to user needs, as initially guided by the programmed server management control console.

Abstract: A fishing rod is strengthened with a metal reinforcement chosen from a metal coating deposited on a formed rod section and a metal wire in a substantially non-crossing arrangement, or a combination of these. In a base section of the rod, wire is wrapped in a single spiral direction so that the wire substantially does not cross itself. In a tip section, wire is arranged to follow the elongated section in a long spiral or substantially linear path, again not substantially crossing itself. The absence of crossing wires allows improved sensitivity and casting accuracy in the rod and eliminates the potential for crossing wires to separate when the rod flexes.

Abstract: The bit rate at which a digital wireless communications system communicates data may be significantly increased by using multiple antennas at both the transmitter and receiver and by decomposing the channel into m subchannels that operate in the same frequency band. The system transmits m one dimensional signals and maximizes the minimum signal-to-noise ratio of the receiver detection process.

Abstract: The bit rate at which a digital wireless communications system communicates data in scattering environments may be significantly increased by using multiple antennas at both the transmitter and receiver and by decomposing the channel into m subchannels. In the same frequency band, m one dimensional signals are transmitted into a scattering environment which makes these transmitted signals appear spatially independent at the receive antenna array. The high bit rate is enabled by special receiver processing to maximize the minimum signal-to-noise ratio of the receiver detection process.

Abstract: A system and method for generating a coherent reference signal for extracting desired user signals from received signals even after error propagation is underway, are presented. A data symbol preceding a sequence whose relative phases are known is used as an absolute phase reference. Since errors in detection of the phase reference symbol are usually caused by error propagation already underway, the sequence can be used to reacquire the desired signal with merely an absolute phase shift in detected data, which allows accurate differential detection of the desired user signal even in the absence of absolute phase knowledge.

Abstract: An apparatus for performance improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal, wherein a plurality of weights is applied to the plurality of received signals producing a plurality of weighted received signals. The plurality of weighted received signals are combined to provide the processed signal. A weight generation circuit generates the plurality of weights wherein weights are based on a given number of interferers.

Abstract: An improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals, and providing a processed signal having an amplitude; and an adjusting circuit for adjusting the amplitude of the processed signal, the adjusting circuit coupled to the processing circuit, where the adjusting circuit adjusts the amplitude as a function of distortion of the plurality of received signals. The processing circuit can weight and combine the plurality of received signals. The distortion can be estimated from a squared error of the plurality of received signals, which can be averaged over a sliding window. The function can comprise multiplying the processed signal by square root of the averaged squared error. Such amplitude adjustment is useful to maintain the soft decision information for the processed signal that is fed to a base station having soft decision decoding, or can be used in the base station with soft decoding.

Abstract: An apparatus for performance improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal, wherein a plurality of weights is applied to the plurality of received signals producing a plurality of weighted received signals. The plurality of weighted received signals are combined to provide the processed signal. A weight generation circuit generates the plurality of weights, wherein weights are generated so as to solve a minimization problem that penalizes excessive time variability in the weights.

Abstract: An apparatus for performance improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal where the received signals are multiplied by weights and combined; and a weight generation circuit for generating the weights; wherein the received signals are sampled at a multiple of a symbol rate, different weights for each set of samples at a symbol rate are generated and the weights are selected to optimize performance.

Abstract: A system and method for applying channel weights in a communication system are presented. The application of weights derived from a sample window is time-shifted into that sample window, decreasing the effects of channel variation and partially compensating for degradation due to differential detection.

Abstract: An apparatus for performance improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal, wherein each of the plurality of received signals is multiplied by a corresponding time-varying complex variate to yield one of a plurality of modified signals, and the plurality of modified signals are then weighed and combined to provide the processed signal; and a generation circuit for generating the corresponding time-varying complex variate.

Abstract: An apparatus for performance improvement of a digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal, wherein each of the plurality of received signals is weighted and combined to provide the processed signal; and a generation circuit for computing a weight vector. The weight vector has a number of weights greater than the plurality of received signals and is computed as a least-squares problem solution.

Abstract: An apparatus for performance improvement of a burst mode digital wireless receiver has a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.