Abstract: A resilient majority driver accepts triple-redundant input signals and provides a robust output signal unaffected by static errors on one of the input signals or by single-event transients caused by radiation within the driver. Data, clock, and asynchronous input signals to DICE (Dual Interlocked storage CEll) flip-flops in a register are driven by resilient majority drivers to construct an input-protected DICE register. Static errors are corrected using triple-redundant inputs and majority voting, while single-event strikes are largely corrected by the DICE architecture within each flip-flop and by the resilient majority drivers. Remaining errors in the input-protected DICE registers, such as those caused by single-event transients occurring during clock transitions, are corrected by error-correction encoders and decoders, whose output transients are suppressed by glitch filters.

Abstract: Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.

Abstract: Systems and methods for shutting down a functional circuit in response to a predetermined total ionizing dose of radiation employ at least two redundant sensing circuits operated in integrate and measure phases by one or more sequencer-type hardware or software controllers. NMOS TID sensors having leakage currents increasing monotonically with dose may be biased during integrate phases, with bias voltages or duty cycles adjusted to achieve a calibrated responsivity. TID measurements are compared to a corresponding reference, latched to generate overexpose signals, and tested for agreement. Disagreement triggers remeasurement to prevent erroneous shutdown until a minimum number of overexpose signals agree that TID exceeds the predetermined threshold. A disable circuit accepts the redundant overexpose signals and generates a signal to disable a functional circuit.

Abstract: Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods will result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Abstract: An integrated circuit for use in high-reliability electronic systems contains one or more digital majority voters with corresponding disagreement detectors connected to the same input signals producing a majority value output and an error signal that is active when not all input signals agree. Internal error signals from multiple majority voter/disagreement detectors as well as external error inputs may be combined using disjunctive error logic to produce an “error detected” output indication. Cold-sparing and hot-plugging are supported by providing cold-sparable electrostatic discharge protection circuits and power-on reset circuitry controlling cold-sparable output stages. Internal modular redundancy provides immunity to single-event transients as well as enhanced reliability.

Abstract: Systems and methods for fault-tolerant threshold circuits used in converting an analog input to a single-bit digital output employ N-modular redundancy of either inverting or non-inverting threshold circuits whose inputs are connected to a single input, and apply majority voting of their outputs to provide correction of transient or permanent faults in up to floor[(N?1)/2] of the individual threshold circuits. Using summation to perform analog majority voting averages the N threshold circuit outputs and provides resilience to single-event transients, but may exhibit an output characteristic having intermediate voltage levels. A digital majority voter having N inputs connected to the outputs of N threshold circuits restores well-defined logic levels and clean hysteresis for Schmitt trigger threshold circuits. A single point of failure at the digital majority voter may be eliminated using an analog majority voter to sum the outputs of three or more redundant digital majority voters.

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Abstract: Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods will result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Abstract: Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency measurements utilize a reference clock. Some measurements count periods of the oscillator signal independently of the reference clock, and some measurements count periods of the reference clock independently of the oscillator signal. After one oscillator on the device has been trimmed, that trimmed oscillator may then be used to make oscillation frequency measurements for trimming another oscillator on the device.

Abstract: Oscillation frequency measurements for trimming oscillators on an integrated circuit device are performed entirely on the device. The oscillation frequency measurements utilize a reference clock. Some measurements count periods of the oscillator signal independently of the reference clock, and some measurements count periods of the reference clock independently of the oscillator signal. After one oscillator on the device has been trimmed, that trimmed oscillator may then be used to make oscillation frequency measurements for trimming another oscillator on the device.

Abstract: Control circuitry for providing a control signal in a pulse width modulating regulating power converter wherein an output parameter delivered by the converter is regulated by pulse width modulation of current within the converter, including circuitry for receiving a sensed output parameter of the converter; circuitry for deriving therefrom an analog average current demand signal corresponding to a current that would bring the converter into regulation; circuitry for receiving a sensed present value of the current within the converter to provide an analog signal representative thereof; circuitry for differencing the average current demand signal and the analog signal to provide an error signal; a compensator arranged to average the error signal to provide a second error signal; a sawtooth generator providing an analog signal as a pulse width modulation ramp; and a comparator to which the ramp is applied to generate the control signal at the output thereof.

Abstract: A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump 40 and a duty cycle detect device 42. When the duty cycle detect device 42 detects that the converter is attempting to operate in 100% duty cycle, the charge pump 40 provides additional charge to the bootstrap capacitor 30 to ensure that the 100% duty cycle is maintained.

Abstract: A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array.

Abstract: An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer.

Abstract: A low gain feedback compensation circuit is provided on an integrated circuit. The feedback compensation circuit is coupled to a step down power supply on the integrated circuit. The step down power supply is operable to receive an input voltage and to generate an output voltage based on the input voltage. The feedback compensation circuit includes a line regulation circuit. The line regulation circuit is operable to receive the input voltage and a reference voltage. The line regulation circuit is also operable to generate an offset voltage based on the input voltage and the reference voltage.

Abstract: A switch mode converter uses the bootstrap capacitor 30 to operate all the way to 100% duty cycle by adding only a very small amount of low-area extra circuitry. The additional circuitry includes a charge pump 40 and a duty cycle detect device 42. When the duty cycle detect device 42 detects that the converter is attempting to operate in 100% duty cycle, the charge pump 40 provides additional charge to the bootstrap capacitor 30 to ensure that the 100% duty cycle is maintained. Performance into dropout (when the input supply is actually lower than the desired output) is improved. A significant advantage in some applications (notably battery operation) is provided.

Abstract: A modulation scheme can drive an associated load that is coupled between a pair of outputs by providing a switching signal at one of the outputs and a non-switching signal at the other output independent of the direction of current relative to the respective outputs. Because switching occurs only at one of the outputs in this mode of operation, a single filter can be used to mitigate switching noise at the switching output. Another aspect relates to another mode of operation in which one or both of the outputs can be controlled to operate linearly, such as during a zero crossing condition, so as to help reduce crossover distortion.