Abstract: The system includes a sensor interface for receiving sensor inputs, a first neural network configured to receive the sensor inputs and provide control signals for controlling the vehicle, and a second neural network configured to receive control signals and provide monitor signals. The system also includes a monitor configured to receive the sensor inputs and the monitor signals and provide a first signal related a proper operation of the first neural network.

Abstract: A dual lock step processor system includes a first processor connected to a first memory, a second processor connected to a second memory, compiler engine, a first instruction engine operably connected to a first memory, and a second instruction engine operably connected to a second memory. The first instruction engine is configured to store a program value; encode the first program value using a first differential encoding and the compiler engine to generate a first encoded program value; and write the first encoded program value into a first address location of a plurality of first address locations. The second instruction engine is configured to store a program value; to encode the first program value using a second differential encoding and the compiler engine to generate a second encoded program value and write the second encoded program value into a second address location of a plurality of second address locations corresponding to the first selected address location.

Abstract: A system can include one or more processors and computer-readable instructions that when executed by the one or more processors, cause the one or more processors to provide a first test signal to an electronic device, monitor at least one parameter of the electronic device during a time period subsequent to the test signal being provided to the electronic device, determine, based on the at least one parameter, a detected response of the electronic device to the first test signal, determine, using a response model, an expected response of the electronic device to the first test signal, and provide a second test signal based on the detected response and the expected response to the electronic device. The system can include a communications circuit that provides the test signal and receives at least some feedback indicating the parameters, and sensors that receive at least some feedback indicating the parameters.

Abstract: A method for indicating the security level of a selected element on a multi-level security display includes determining a security level of a selected element and modifying the visual representation of the selected element to indicate the security level and/or providing an audible tone. Visual distinction may include a security tag, color variation or flashing pattern.

Abstract: The present invention is a method for providing a high-assurance guard in a partitioned processing system, the partitioned processing system including a first input/output partition, a guard function partition and a second input/output partition, the method including the steps of: receiving a data packet from the first input/output partition of the partitioned processing system via a first I/O interface; determining if the data packet is well-formed as defined by an interface control document; and forwarding the data packet to the second input/output partition of the partitioned processing system and to a second I/O interface only when the data packet is well-formed.

Abstract: A system and method for enhancing the integrity of an avionics system which uses a pair dissimilar general purpose microprocessors, each running a virtual machine, compiled for its respective processor, from a common original source file; the virtual machines running on a subset of the instructions for each microprocessor and thereby avoiding conditions known or likely to result in defects; the virtual machines running a single or identical avionics program and then voting the results of this simultaneous redundant execution to arrive at an enhanced assurance level; providing written claims to the FAA that an enhanced assurance level is achieved.

Abstract: Multiple Java Virtual Machines (JVMs) operate on a single direct execution JAVA processor with each JVM operating in a separate time slice called a partition. Each JVM has its own data and control structures and is assigned a fixed area of memory. Each partition is also allotted a fixed period of time in which to operate, and, at the end of the allotted time, a context switch is forced to another JVM operating in the next partition. The context switch does not transfer control directly from one JVM to another JVM. Instead, at the end of a partition time period control is switched from the currently operating JVM to a “master JVM” during a time period called an “interstice.” The master JVM handles system interrupts and housekeeping duties. At the end of the interstice time period, the master JVM starts a proxy thread associated with the next JVM to become operational. The proxy thread handles JVM-specific interrupts and checks the status of the associated JVM.

Abstract: An improved computer architecture and system advantageously combine the beneficial characteristics of a high level object oriented programming language with an optimized processor for efficient application to real time embedded computing problems. Additionally, an improved method for resolving symbolic references in code generated by compiling source code written in an object oriented programming language to the corresponding logical memory addresses stores look-up information with the object itself after the first encounter of a given symbolic reference, whereby the logical memory address information is available for subsequent encounters of the symbolic reference, and whereby no modification of the program instructions containing the symbolic reference is necessary. In a preferred embodiment, the Java™ programming language is used.

Abstract: A passive matrix liquid crystal display and a method of driving the same are provided. A desired RMS voltage to be achieved during a first frame is determined for each pixel element of the display. A modulation coefficient is determined for each pixel element as a function of the desired RMS voltage for the pixel element during the first frame. For each cycle of the frame, a phase delay is determined for each column drive waveform as a function of the sum, over all rows, of the product of each modulation coefficient of a pixel element in the column and the phase delay of the corresponding row drive waveform during the cycle.