Patents by Inventor David A. Heisley

David A. Heisley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130043934
    Abstract: An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.
    Type: Application
    Filed: August 17, 2011
    Publication date: February 21, 2013
    Inventors: David A. Heisley, Allan T. Mitchell
  • Patent number: 6333623
    Abstract: A low drop-out (“LDO”) voltage regulator includes an output stage of having a pass device and a discharge device arranged in complementary voltage follower configurations to both source load current to and sink load current from a regulated output voltage conductor. The pass device and the discharge device are controlled through a single feedback loop.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: December 25, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Heisley, Tony R. Larson
  • Patent number: 6201375
    Abstract: An LDO voltage regulator includes an error amplifier having a first input coupled to a first reference voltage, a second input receiving a feedback signal, and an output producing a first control signal. An output transistor has a gate, a drain coupled to an unregulated input voltage, and a source coupled to produce a regulated output voltage on an output conductor. A feedback circuit is coupled between the output conductor and a second reference voltage. An overvoltage comparator has a first input coupled to receive the first reference voltage and a second input coupled to respond to the feedback signal to produce a discharge control signal indicating occurrence of an output overvoltage of at least a predetermined magnitude to control a discharge transistor coupled between the output conductor and the second reference voltage. An output current sensing circuit produces a control current representative of the drain current of the output transistor.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: March 13, 2001
    Assignee: Burr-Brown Corporation
    Inventors: Tony R. Larson, David A. Heisley
  • Patent number: 6188212
    Abstract: A low drop out voltage regulator includes an error amplifier (12) having a first input coupled to a first reference voltage (VREF), a second input receiving a feedback signal, and an output (15) producing an output signal (VAMPOUT). An output transistor (18) has a gate, a drain coupled to an unregulated input voltage (VIN), and a source coupled to produce a regulated output voltage (VOUT) on an output conductor (19). A feedback circuit (20,22) is coupled between the output conductor (19) and a reference voltage (GND) to produce the feedback signal. A capacitor (16) is coupled between the output (15) of the error amplifier and the gate (17) of the output transistor (18). A servo amplifier (24) has a first input coupled to a second reference voltage (VVREF), a second input coupled to the output (15) of the error amplifier. A low current charge pump circuit (26B) supplies an output current into a supply voltage terminal of the servo amplifier.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: February 13, 2001
    Assignee: Burr-Brown Corporation
    Inventors: Tony R. Larson, David A. Heisley, R. Mark Stitt, Rodney T. Burt
  • Patent number: 4999585
    Abstract: Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor.
    Type: Grant
    Filed: November 6, 1989
    Date of Patent: March 12, 1991
    Assignee: Burr-Brown Corporation
    Inventors: Rodney T. Burt, Timothy V. Kalthoff, David A. Heisley, R. Mark Stitt, II