Abstract: A test and measurement instrument can include an input to receive an analog signal, a sampler to produce digital sample data corresponding to the analog signal, a buffer to store a portion of the sample data, a memory to store sample data from the buffer, a plurality of comparators to establish a vertical range, and a controller configured to configure the plurality of comparators to establish a first vertical range based on sample data in the buffer, and determine whether any of the sample data in the buffer transitions outside the first vertical range during a period of time.

Abstract: A test and measurement instrument can include an input to receive an analog signal, a sampler to produce digital sample data corresponding to the analog signal, a buffer to store a portion of the sample data, a memory to store sample data from the buffer, a plurality of comparators to establish a vertical range, and a controller configured to configure the plurality of comparators to establish a first vertical range based on sample data in the buffer, and determine whether any of the sample data in the buffer transitions outside the first vertical range during a period of time.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: A test and measurement instrument such as a Logic Analyzer, or the like, has at least one Reloadable Word Recognizer whose reference value can be loaded by a trigger machine with a current acquired data sample while data is being acquired. In a second embodiment useful for performing memory testing, the reloadable word recognizer is used in cooperation with two conventional word recognizers. In a third embodiment, a delay unit is employed to provide delayed input data words as reference words. In a fourth embodiment, an offset register and adder are used to modify the input data words before storing them. A fifth embodiment provides for substantially immediate use of base addresses of relocatable subroutines and stack-based variables recovered from a data stream acquired from a system under test.

Abstract: A word recognizer for providing a channel-to-channel compare for an input digital signal divides channels of the input digital signal into equal-width input signal channel paths. One input signal channel path serves as a reference value for comparison with the other input signal channel path to produce the channel-to-channel compare.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: A word recognizer for providing a channel-to-channel compare for an input digital signal divides channels of the input digital signal into equal-width input signal channel paths. One input signal channel path serves as a reference value for comparison with the other input signal channel path to produce the channel-to-channel compare.

Abstract: A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of other, different, events. Both an overflow (incremented to a predetermined count) and an underflow (decremented to a predetermined count) can be tested by a trigger machine of the Logic Analyzer.

Abstract: An electronic system includes a source of test data, which, if the test data source is operating properly, is a pattern of a limited number of data words successively repeated. A memory device is coupled to the test data source and stores the test data. A memory test circuit compares the stored test data to successively repeated pattern data words and generates a signal to indicate whether the stored test data is the same as the successively repeated pattern data words.

Abstract: A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of other, different, events. Both an overflow (incremented to a predetermined count) and an underflow (decremented to a predetermined count) can be tested by a trigger machine of the Logic Analyzer.

Abstract: A test and measurement instrument such as a Logic Analyzer, or the like, has at least one Reloadable Word Recognizer whose reference value can be loaded by a trigger machine with a current acquired data sample while data is being acquired. In a second embodiment useful for performing memory testing, the reloadable word recognizer is used in cooperation with two conventional word recognizers. In a third embodiment, a delay unit is employed to provide delayed input data words as reference words. In a fourth embodiment, an offset register and adder are used to modify the input data words before storing them. A fifth embodiment provides for substantially immediate use of base addresses of relocatable subroutines and stack-based variables recovered from a data stream acquired from a system under test.

Abstract: In a logic analyzer or similar binary signal-analyzing instrument, hardware circuitry, such as an ASIC, or other dedicated hardware, is used to perform waveform compression and summarization more rapidly than it could be done by software alone. The hardware is used to perform the compression of the data and to summarize its behavior for visual display. In one embodiment, the hardware starts from a given memory address and compares current timestamp values with final timestamp values to determine the length of the timeslice. Within the timeslice, all of the data is compared to determine whether it remains the same throughout the timeslice or whether it changes. The same approach can be used on violation data, such as glitches and setup and hold violations.