Abstract: A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable memory (CAM) receives the hashed output value, and in response, provides an index value and activates a hit signal if the hashed output value matches an entry of the CAM. A random access memory (RAM) receives the index value from the CAM. The RAM stores a collision resolution value and information associated with the character string in an entry associated with the index value. The RAM provides this information and collision resolution value in response to the index value. Logic circuitry indicates a collision if the hit signal is activated and the collision resolution value provided by the hardware hashing circuit does not match the collision resolution value provided by the RAM.