Patents by Inventor David A. Hrusecky
David A. Hrusecky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10552165Abstract: Within a processor, speculative finishes of load instructions only are tracked in a speculative finish table by maintaining an oldest load instruction of a thread in the speculative finish table after data is loaded for the oldest load instruction, wherein a particular queue index tag assigned to the oldest load instruction by an execution unit points to a particular entry in the speculative finish table, wherein the oldest load instruction is waiting to be finished dependent upon an error check code result. Responsive to a flow unit receiving the particular queue index tag with an indicator that the error check code result for data retrieved for the oldest load instruction is good, finishing the oldest load instruction in the particular entry pointed to by the queue index tag and writing an instruction tag stored in the entry for the oldest load instruction out of the speculative finish table for completion.Type: GrantFiled: October 19, 2015Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward
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Publication number: 20190384602Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Patent number: 10496406Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: June 21, 2018Date of Patent: December 3, 2019Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10423423Abstract: Within a processor, speculative finishes of load instructions only are tracked in a speculative finish table by maintaining an oldest load instruction of a thread in the speculative finish table after data is loaded for the oldest load instruction, wherein a particular queue index tag assigned to the oldest load instruction by an execution unit points to a particular entry in the speculative finish table, wherein the oldest load instruction is waiting to be finished dependent upon an error check code result. Responsive to a flow unit receiving the particular queue index tag with an indicator that the error check code result for data retrieved for the oldest load instruction is good, finishing the oldest load instruction in the particular entry pointed to by the queue index tag and writing an instruction tag stored in the entry for the oldest load instruction out of the speculative finish table for completion.Type: GrantFiled: September 29, 2015Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward
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Publication number: 20190286446Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, Jr.
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Patent number: 10409598Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: June 21, 2018Date of Patent: September 10, 2019Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10318419Abstract: Flush avoidance in a load store unit including launching a load instruction targeting an effective address; encountering a set predict hit and an effective-to-real address translator (ERAT) miss for the effective address, wherein the set predict hit comprises a cache address of a cache entry; sending a data valid message for the load instruction to an instruction sequencing unit; and verifying the data valid message, wherein verifying the data valid message comprises: tracking the cache entry during an ERAT update; and upon completion of the ERAT update, encountering an ERAT hit for the effective address in response to relaunching the load instruction.Type: GrantFiled: August 8, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Sundeep Chadha, David A. Hrusecky, Elizabeth A. McGlone, George W. Rohrbaugh, III, Shih-Hsiung S. Tung
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Patent number: 10268518Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.Type: GrantFiled: June 5, 2018Date of Patent: April 23, 2019Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone
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Patent number: 10255107Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.Type: GrantFiled: June 1, 2018Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone
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Patent number: 10169046Abstract: An instruction sequencing unit in an out-of-order (OOO) processor includes a Most Favored Instruction (MFI) mechanism that designates an instruction as an MFI. The processing queues in the processor identify when they contain the MFI, and assures processing the MFI. The MFI remains the MFI until it is completed or is flushed, and which time the MFI mechanism selects the next MFI.Type: GrantFiled: August 31, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr., Kenneth L. Ward
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Publication number: 20180300135Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: June 21, 2018Publication date: October 18, 2018Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Publication number: 20180300136Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: June 21, 2018Publication date: October 18, 2018Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Publication number: 20180293077Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where each load/store slice includes a load miss queue and a load reorder queue, includes: receiving, at a load reorder queue, a load instruction requesting data; responsive to the data not being stored in a data cache, determining whether a previous load instruction is pending a fetch of a cache line comprising the data; if the cache line does not comprise the data, allocating an entry for the load instruction in the load miss queue; and if the cache line does comprise the data: merging, in the load reorder queue, the load instruction with an entry for the previous load instruction.Type: ApplicationFiled: June 8, 2018Publication date: October 11, 2018Inventors: KIMBERLY M. FERNSLER, DAVID A. HRUSECKY, HUNG Q. LE, ELIZABETH A. MCGLONE, BRIAN W. THOMPTO
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Publication number: 20180285161Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.Type: ApplicationFiled: June 5, 2018Publication date: October 4, 2018Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, ELIZABETH A. MCGLONE
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Publication number: 20180276132Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.Type: ApplicationFiled: June 1, 2018Publication date: September 27, 2018Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, ELIZABETH A. MCGLONE
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Publication number: 20180260230Abstract: Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.Type: ApplicationFiled: May 15, 2018Publication date: September 13, 2018Inventors: RICHARD J. EICKEMEYER, DAVID A. HRUSECKY, ELIZABETH A. MCGLONE, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Patent number: 10073697Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: February 18, 2016Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10067763Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: GrantFiled: December 11, 2015Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10042647Abstract: Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.Type: GrantFiled: June 27, 2016Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Richard J. Eickemeyer, David A. Hrusecky, Elizabeth A. McGlone, Brian W. Thompto, Albert J. Van Norstrand, Jr.
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Patent number: 10042770Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.Type: GrantFiled: July 27, 2016Date of Patent: August 7, 2018Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone