Abstract: An SRAM cell comprises a first inverter having an output lead coupled to the input lead of a second inverter via a first resistor. The output lead of the second inverter is coupled to the first inverter input lead via a second resistor. A first write bit line is coupled to the first inverter input lead via a first switch, and a second write bit line is coupled to the second inverter input lead via a second switch. Because of the resistors, the circuitry driving write bit lines does not have to overpower the inverters when writing data to the cell. The cell is part of an array comprising several columns of SRAM cells, each column coupled to a pair of write bit lines. A resonating oscillator drives the write bit lines with a sine wave. This reduces the power consumed by the SRAM array.

Abstract: A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.

Abstract: An SRAM cell comprises a first inverter having an output lead coupled to the input lead of a second inverter via a first resistor. The output lead of the second inverter is coupled to the first inverter input lead via a second resistor. A first write bit line is coupled to the first inverter input lead via a first switch, and a second write bit line is coupled to the second inverter input lead via a second switch. Because of the resistors, the circuitry driving write bit lines does not have to overpower the inverters when writing data to the cell. The cell is part of an array comprising several columns of SRAM cells, each column coupled to a pair of write bit lines. A resonating oscillator drives the write bit lines with a sine wave. This reduces the power consumed by the SRAM array.

Abstract: A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.

Abstract: A solid-state video surveillance system includes at least two video cameras and a video controller unit. The video controller unit synchronizes the operation of the video cameras such that video data may be independently generated from each of the cameras substantially in phase. The video data from each of the cameras may be merged and stored in a data file. The data file is a continuous loop such that newly stored video data continuously overwrites the oldest previously stored video data. The data file may be stored in a detachable solid state memory device.