Patents by Inventor David A. Jaffe
David A. Jaffe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090148842Abstract: The invention relates to a method of preparing and using a library of template polynucleotides suitable for use as templates in solid-phase nucleic acid amplification and sequencing reactions to determine the methylation status of the cytosine bases in the library. In particular, the invention relates to a method of preparing and analysing a library of template polynucleotides suitable for methylation analysis.Type: ApplicationFiled: February 7, 2008Publication date: June 11, 2009Inventors: Niall Gormley, Andreas Gnirke, David Jaffe, Harris Nusbaum
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Publication number: 20090121287Abstract: A semiconductor device having wiring levels on opposite sides, a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides, and a design structure of a semiconductor device having wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Publication number: 20090121260Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Publication number: 20090065925Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: ApplicationFiled: August 6, 2008Publication date: March 12, 2009Inventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Patent number: 7492048Abstract: Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.Type: GrantFiled: January 10, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James William Adkisson, Jeffrey Peter Gambino, Mark David Jaffe, Jeffrey Bowman Johnson, Jerome Brett Lasky, Richard John Rassel
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Publication number: 20080308948Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: ApplicationFiled: August 26, 2008Publication date: December 18, 2008Inventors: Thomas Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Patent number: 7462509Abstract: An method of packaging an electronic device. The method for packaging the device including: providing a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: GrantFiled: May 16, 2006Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Publication number: 20080213948Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: February 12, 2008Publication date: September 4, 2008Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Publication number: 20080128812Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: ApplicationFiled: February 12, 2008Publication date: June 5, 2008Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Patent number: 7381627Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: GrantFiled: July 9, 2007Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Publication number: 20070267746Abstract: An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventors: Kerry Bernstein, Timothy Dalton, Timothy Harrison Daubenspeck, Jeffrey Peter Gambino, Mark David Jaffe, Christopher David Muzzy, Wolfgang Sauter, Edmund Sprogis, Anthony Kendall Stamper
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Publication number: 20070267723Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Stephen Ellinwood Luce, Anthony Kendall Stamper
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Patent number: 7285477Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.Type: GrantFiled: May 16, 2006Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Paul David Kartschoke, Anthony Kendall Stamper
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Patent number: 7193423Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10?18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.Type: GrantFiled: December 12, 2005Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: Timothy Joseph Dalton, Jeffrey Peter Gambino, Mark David Jaffe, Stephen Ellinwood Luce, Edmund Juris Sprogis
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Publication number: 20030174147Abstract: A device, system and method may simulate a virtual model or modeling platform. A device, system and method for simulating a physical system such as a virtual simulation, living being, machine, etc., is capable of placing a set of virtual objects into a virtual work space, the virtual work space typically having a set of global definitions, simulating the interaction of the virtual objects and virtual work space, and displaying the simulated interaction. The device, system and method may include the capability of authoring a virtual simulation or experiment. A device, system or method may define a set of virtual objects and a virtual work space, the virtual objects having object parameters and the virtual work space having a set of global parameters, and place into a simulation data file the virtual experiment objects and said virtual work space. A student or researcher may conduct a virtual experiment using a computer system.Type: ApplicationFiled: February 13, 2003Publication date: September 18, 2003Inventor: David Jaffe
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Publication number: 20030066026Abstract: The present invention includes a virtual experiment authoring application and a virtual experiment presentation application. As part of the present invention, at least two virtual experiment objects, each object including a data structure with at least one parameter defining a physical characteristic of the virtual experiment object, may be placed within a virtual work space in an arrangement defining an initial state of a system formed by the at least two virtual experiment objects. The virtual work space may include at least one global parameter, and a translation module which may derive at least one equation defining a mathematical model of a system formed by the at least two virtual experiment objects within the virtual environment. Also included in the present invention may be a virtual lab area and a simulation engine.Type: ApplicationFiled: August 13, 2002Publication date: April 3, 2003Inventor: David Jaffe
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Patent number: 5781461Abstract: A sampled data, delay line structure that includes a sampled data delay line, two readers for reading data at corresponding positions of the delay line, controller that controls when the read position of each reader is updated for a new note of a different pitch, and a crossfader that crossfades between the outputs of the two readers to produce a legato transition between the two discrete notes associated with the two readers. The controller receives a control signal indicating a sequence of note events to be implemented by the delay line structure. When a new note on event occurs while a previous note is still playing, a legato crossfade sequence is performed. In particular, the delay line reader not used by the previous note is set to a delay position associated with the new note, and the crossfader is enabled. The crossfader gradually transitions its output from that of the reader used for the previous note to the output of the reader used from the new note.Type: GrantFiled: September 4, 1996Date of Patent: July 14, 1998Assignee: Board of Trustees of the Leland Stanford Junior UniversityInventors: David A. Jaffe, Julius O. Smith, III
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System and method for generating fractional length delay lines in a digital signal processing system
Patent number: 5742532Abstract: A sampled data, non-integer delay line interpolation structure includes a sampled data delay line, two allpass filters, each having an associated read pointer for reading data at a corresponding integer position of the delay line, an alternating crossfader that alternatingly crossfades between the outputs of the two allpass filters, plus a controller that controls when the read position of each allpass filter is updated and also controls when the filter coefficient of each allpass filter is updated. A specified delay length value is sampled by the controller each time the crossfade orientation of the alternating crossfader is changed, and from that value the controller generates a new read pointer and filter coefficient for allpass filter to which the structure will next crossfade. The new read pointer is an integer that corresponds to an integer portion of the specified delay length, and the filter coefficient corresponds to a fractional portion of the specified delay length.Type: GrantFiled: May 9, 1996Date of Patent: April 21, 1998Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Scott A. Van Duyne, David A. Jaffe, Gregory P. Scandalis, Timothy S. Stilson