Patents by Inventor David A. Jandzinski
David A. Jandzinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9899350Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.Type: GrantFiled: August 5, 2016Date of Patent: February 20, 2018Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick
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Patent number: 9892937Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: February 13, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9859132Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: June 3, 2016Date of Patent: January 2, 2018Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Publication number: 20170334710Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.Type: ApplicationFiled: May 22, 2017Publication date: November 23, 2017Inventors: Julio C. Costa, Jon Chadwick, David Jandzinski, Merrill Albert Hatcher, Jr., Jonathan Hale Hammond
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Patent number: 9613831Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: December 4, 2015Date of Patent: April 4, 2017Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Patent number: 9576822Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: GrantFiled: December 4, 2015Date of Patent: February 21, 2017Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Publication number: 20160343592Abstract: A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.Type: ApplicationFiled: August 5, 2016Publication date: November 24, 2016Inventors: Julio C. Costa, Thomas Scott Morris, Jonathan Hale Hammond, David Jandzinski, Stephen Parker, Jon Chadwick
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Publication number: 20160284570Abstract: The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.Type: ApplicationFiled: June 3, 2016Publication date: September 29, 2016Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Publication number: 20160284568Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.Type: ApplicationFiled: December 4, 2015Publication date: September 29, 2016Inventors: Thomas Scott Morris, David Jandzinski, Stephen Parker, Jon Chadwick, Julio C. Costa
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Publication number: 20140146489Abstract: An electronic substrate includes a non-conductive body and one or more conductive features coupled to the non-conductive body. Each of the conductive features includes a base layer. To preserve the performance and conductivity of the one or more conductive features, each of the conductive features includes a protective layer formed over the base layer. The protective layer may include a first layer of silver formed over the base layer and a second layer of palladium formed over the first layer. By depositing the protective layer over the base layer of each of the conductive features, oxidation and exposure of the conductive features is prevented, or at least substantially reduced, since the first layer and the second layer provide a migration barrier for the metal in the base layer. However, the performance and conductivity of the conductive features are maintained due to the low resistivity of silver and palladium.Type: ApplicationFiled: May 10, 2013Publication date: May 29, 2014Inventors: John August Orlowski, Donald Joseph Leahy, Thomas Scott Morris, David C. Dening, David Jandzinski
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Publication number: 20140106564Abstract: A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.Type: ApplicationFiled: March 26, 2013Publication date: April 17, 2014Applicant: RF Micro Devices, Inc.Inventors: John August Orlowski, David Jandzinski
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Patent number: 8409658Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: GrantFiled: December 7, 2007Date of Patent: April 2, 2013Assignee: RF Micro Devices, Inc.Inventors: David J. Hiner, Waite R. Warren, Jr., David Jandzinski
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Patent number: 8296941Abstract: A meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: GrantFiled: May 27, 2011Date of Patent: October 30, 2012Assignee: RF Micro Devices, Inc.Inventors: David J. Hiner, Waite R. Warren, Jr., Donald Joseph Leahy, David Jandzinski, Thomas Scott Morris, David Halchin, Milind Shah, Mark Charles Held, Brian Howard Calhoun, Brian D. Sawyer, Ulrik Riis Madsen
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Publication number: 20110225803Abstract: A meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: ApplicationFiled: May 27, 2011Publication date: September 22, 2011Applicant: RF MICRO DEVICES, INC.Inventors: David J. Hiner, Waite R. Warren, JR., Donald Joseph Leahy, David Jandzinski, Thomas Scott Morris, David Halchin, Milind Shah, Mark Charles Held, Brian Howard Calhoun, Brian D. Sawyer, Ulrik Riis Madsen
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Publication number: 20100199492Abstract: A meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: ApplicationFiled: April 23, 2010Publication date: August 12, 2010Applicant: RF MICRO DEVICES, INC.Inventors: David J. Hiner, Waite R. Warren, JR., Donald Joseph Leahy, David Jandzinski, Thomas Scott Morris, David Halchin, Milind Shah, Mark Charles Held, Brian Howard Calhoun, Brian D. Sawyer, Ulrik Riis Madsen
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Publication number: 20090000815Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: ApplicationFiled: December 7, 2007Publication date: January 1, 2009Applicant: RF MICRO DEVICES, INC.Inventors: David J. Hiner, Waite R. Warren, JR., Donald Joseph Leahy, David Jandzinski, Thomas Scott Morris, David Halchin, Milind Shah, Mark Charles Held, Brian Howard Calhoun, Brian D. Sawyer, Ulrik Riis Madsen
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Publication number: 20090000816Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a portion of the metallic structure for each component area to be shielded is then exposed through the body by a cutting, drilling, or like operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed portion of the metallic structures.Type: ApplicationFiled: December 7, 2007Publication date: January 1, 2009Applicant: RF MICRO DEVICES, INC.Inventors: David J. Hiner, Waite R. Warren, Jr., David Jandzinski
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Patent number: 6992100Abstract: A novel class of tetracyclic compounds is disclosed together with the use of such compounds for inhibiting sPLA2 mediated release of fatty acids for treatment of Inflammatory Diseases such as septic shock.Type: GrantFiled: December 6, 2001Date of Patent: January 31, 2006Assignee: Eli Lilly and CompanyInventors: Douglas Wade Beight, Michael Dean Kinnick, Ho-Shen Lin, John Michael Morin, Jr., Michael Enrico Richett, Daniel Jon Sall, Jason Scott Sawyer, John David Jandzinski
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Publication number: 20040092543Abstract: A novel class of tetracyclic compounds is disclosed together with the use of such compounds for inhibiting sPLA2 mediated release of fatty acids for treatment of Inflammatory Diseases such as septic shock.Type: ApplicationFiled: June 16, 2003Publication date: May 13, 2004Inventors: Douglas Wade Beight, Michael Dean Kinnick, Ho-Shen Lin, John Michael Morin Jr, Michael Enrico Richett, Daniel Jon Sall, Jason Scott Sawyer, John David Jandzinski
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Patent number: 5892661Abstract: A smartcard (10) is formed in part by a laminate layer (77). The laminate layer (77) is made up of a plurality of dielectric layers (11,30), insulating layers (45, 50), resistive layers (55), and electrically active structures. The electrically active structures include a capacitive structure (23) which is formed from one of the dielectric layers (11) and an antennae (32) which is made from a conductive layer that is formed into a spiral pattern on the another dielectric layer (30). These layers (11,30, 45, 50, 55) are formed separately and then pressed together to form the laminate layer (77).Type: GrantFiled: October 31, 1996Date of Patent: April 6, 1999Assignee: Motorola, Inc.Inventors: John W. Stafford, Theodore G. Tessier, David A. Jandzinski