Patents by Inventor David A. Jefferson
David A. Jefferson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10871749Abstract: Methods and systems are provided for scheduling an alarm wake up to self-wake a control module of a vehicle while the vehicle is off to perform requesting features, including diagnostic and non-diagnostic afterrun tasks. In one example, a method may include, during a shutdown event of the control module, querying a plurality of requesting features for alarm wake up times, receiving a plurality of alarm wake up times from the plurality of requesting features, selecting one alarm wake up time from the plurality of alarm wake up times received, and setting a timer for the selected alarm wake up time. When the timer elapses at the selected alarm wake up time, the control module is woken and a request to run is sent to each of the plurality of requesting features.Type: GrantFiled: November 8, 2017Date of Patent: December 22, 2020Assignee: Ford Global Technologies, LLCInventors: Robert Roy Jentz, Sanyam Sharma, Eric David Jefferson, Hugh Hamilton
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Publication number: 20190137940Abstract: Methods and systems are provided for scheduling an alarm wake up to self-wake a control module of a vehicle while the vehicle is off to perform requesting features, including diagnostic and non-diagnostic afterrun tasks. In one example, a method may include, during a shutdown event of the control module, querying a plurality of requesting features for alarm wake up times, receiving a plurality of alarm wake up times from the plurality of requesting features, selecting one alarm wake up time from the plurality of alarm wake up times received, and setting a timer for the selected alarm wake up time. When the timer elapses at the selected alarm wake up time, the control module is woken and a request to run is sent to each of the plurality of requesting features.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Inventors: Robert Roy Jentz, Sanyam Sharma, Eric David Jefferson, Hugh Hamilton
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Patent number: 9208357Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: August 28, 2014Date of Patent: December 8, 2015Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Patent number: 9054859Abstract: Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.Type: GrantFiled: April 29, 2014Date of Patent: June 9, 2015Assignee: Altera CorporationInventors: Keone Streicher, David Jefferson, Juju Joyce, Martin Langhammer
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Patent number: 8826038Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: May 18, 2012Date of Patent: September 2, 2014Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Patent number: 8750503Abstract: Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.Type: GrantFiled: January 25, 2013Date of Patent: June 10, 2014Assignee: Altera CorporationInventors: Keone Streicher, David Jefferson, Juju Joyce, Martin Langhammer
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Patent number: 8433930Abstract: Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.Type: GrantFiled: September 17, 2010Date of Patent: April 30, 2013Assignee: Altera CorporationInventors: Juju Joyce, Martin Langhammer, Keone Streicher, David Jefferson
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Patent number: 8363833Abstract: Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.Type: GrantFiled: June 8, 2011Date of Patent: January 29, 2013Assignee: Altera CorporationInventors: Keone Streicher, David Jefferson, Juju Joyce, Martin Langhammer
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Patent number: 8209545Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: May 21, 2010Date of Patent: June 26, 2012Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Patent number: 7984292Abstract: Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.Type: GrantFiled: September 14, 2009Date of Patent: July 19, 2011Assignee: Altera CorporationInventors: Keone Streicher, David Jefferson, Juju Joyce, Martin Langhammer
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Patent number: 7818584Abstract: Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.Type: GrantFiled: January 25, 2005Date of Patent: October 19, 2010Assignee: Altera CorporationInventors: Juju Joyce, Martin Langhammer, Keone Streicher, David Jefferson
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Patent number: 7734043Abstract: Circuits, methods, and apparatus that prevent easy detection and erasure or modification of an encryption or encoding key. This key may be used to encode and decode a configuration bitstream for an FPGA or other programmable or configurable device. One embodiment of the present invention obfuscates a key then stores it in a memory array on an FPGA. This memory array may be a one-time programmable memory to prevent erasure or modification of the key. After retrieval from storage, a reverse or de-obfuscation is performed to recover the key. Further obfuscation may be achieved by proper layout of the relevant circuitry.Type: GrantFiled: January 25, 2005Date of Patent: June 8, 2010Assignee: Altera CorporationInventors: David Jefferson, Martin Langhammer, Keone Streicher, Juju Joyce
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Patent number: 7725738Abstract: Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.Type: GrantFiled: January 25, 2005Date of Patent: May 25, 2010Assignee: Altera CorporationInventors: Martin Langhammer, Juju Joyce, Keone Streicher, David Jefferson, Srinivas Reddy, Nitin Prasad
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Patent number: 7606362Abstract: Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.Type: GrantFiled: January 25, 2005Date of Patent: October 20, 2009Assignee: Altera CorporationInventors: Keone Streicher, David Jefferson, Juju Joyce, Martin Langhammer
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Patent number: 7606081Abstract: A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder coupled to the plurality of selectors.Type: GrantFiled: November 19, 2008Date of Patent: October 20, 2009Assignee: Altera CorporationInventor: David Jefferson
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Patent number: 7463544Abstract: A device that is programmable to operate as a memory device, a multiplexer, or a demultiplexer includes: a first column decoder; a memory array coupled to the first column decoder; a plurality of selectors coupled to the memory array; and a second column decoder coupled to the plurality of selectors.Type: GrantFiled: June 2, 2003Date of Patent: December 9, 2008Assignee: Altera CorporationInventor: David Jefferson
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Patent number: 7343470Abstract: Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.Type: GrantFiled: September 26, 2003Date of Patent: March 11, 2008Assignee: Altera CorporationInventors: Juju Joyce, Dan Mansur, David Jefferson, Changsong Zhang, Yi-Wen Lin
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Patent number: 7228451Abstract: A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.Type: GrantFiled: November 8, 2005Date of Patent: June 5, 2007Assignee: Altera CorporationInventors: Triet Nguyen, David Jefferson, Srinivas Reddy, Keone Streicher
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Patent number: 7161381Abstract: A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.Type: GrantFiled: February 25, 2004Date of Patent: January 9, 2007Assignee: Altera CorporationInventors: Srinivas Reddy, David Jefferson, Christopher F. Lane, Vikram Santurkar, Richard Cliff
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Patent number: 7051153Abstract: A memory array configured to operate as a shift register includes a first column of memory cells with an input and an output and at least a second column of memory cells with an input and an output. The memory array also includes a multiplexer that is connected between the output of the first column of memory cells and the input of the second column of memory cells. The memory array can be operated as a shift register by shifting data from the first column of memory cells to the second column of memory cells through the multiplexer rather than using general routing lines.Type: GrantFiled: May 6, 2002Date of Patent: May 23, 2006Assignee: Altera CorporationInventors: Yi-Wen Lin, Changsong Zhang, David Jefferson, Srinivas Reddy