Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract: A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.

Abstract: An RFID transponder chip includes at least one antenna to pick-up and transmit radio-frequency signals, a rectifier to store charge on at least one capacitor at a rectified voltage from the picked-up radio-frequency signals, a power-on reset circuit to maintain a logic unit in a reset state if the rectified voltage level is less than a power-on reset or wake-up voltage of the power-on reset circuit for operating the logic unit. The RFID transponder chip further includes a non-volatile memory, in which are stored one or several trim values. Said non-volatile memory is directly connected to the power-on reset circuit to be able to provide at least one trim value to trim the power-on reset circuit at a rectified voltage level below a wake-up voltage level.

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit formed by at least a NVM cell and a sensor activated by a physical or chemical action or phenomenon, the NVM unit arranged for storing in the NVM cell, by using electrical power of the electrical stimulus pulse, a bit of information relative to detection by the sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal and a base terminal of the NVM unit with at least a given set voltage.

Abstract: The self-powered detection device comprises a non-volatile memory cell and a sensor activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester transforming energy from the physical or chemical action orphenomenon into an electrical stimulus pulse, the memory cell arranged for storing, by using electrical power of the electrical stimulus pulse, at least a bit of information relative to detection by the sensor of at least a first physical or chemical action or phenomenon. The non-volatile memory cell comprises a FET transistor having a control gate, a first diffusion defining a first input and a second diffusion defining a second input. This FET transistor is set to its written logical state from its initial logical state when, in a detection mode, it receives on a set terminal a voltage stimulus signal resulting from the first physical or chemical action or phenomenon.

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage.

Abstract: A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed by at least a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, the NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of the NVM unit with at least a given set voltage.

Abstract: The self-powered detection device comprises a Non-Volatile Memory (NVM) unit (52) formed at least by a NVM cell and a sensor which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, said NVM unit being arranged for storing in said NVM cell, by using the electrical power of said electrical stimulus pulse, a bit of information relative to the detection by said sensor, during a detection mode of the self-powered detection device, of at least one physical or chemical action or phenomenon applied to it with at least a given strength or intensity and resulting in a voltage stimulus signal provided between a set control terminal (SET) and a base terminal (SET *) of said NVM unit with at least a given set voltage.

Abstract: The self-powered detection device comprises at least a non-volatile memory cell (24) and a sensor (16) which is activated by a physical or chemical action or phenomenon, this sensor forming an energy harvester that transforms energy from said physical or chemical action or phenomenon into an electrical stimulus pulse, the memory cell being arranged for storing, by using the electrical power of said electrical stimulus pulse, at least a bit of information relative to the detection by the sensor of at least a first physical or chemical action or phenomenon applied to it with at least a given strength or intensity. The non-volatile memory cell is formed by a FET transistor (T1) having a control gate, a first diffusion (DRN) defining a first input and a second diffusion (SRC) defining a second input.

Abstract: The external event detection device comprises an electronic unit (22) and an external event sensor (16), the electronic unit having at least a non-volatile memory cell (24, T1) in which data relative to at least one external event detected by the external event sensor can be stored. According to the invention, the external event sensor defines an energy harvester that transforms energy from said at least one external event into electrical energy contained in an electrical stimulus pulse provided to the electronic unit. The electronic unit is arranged for storing said data by using only the electrical energy contained in the electrical stimulus pulse. In particular, the non-volatile memory cell is directly set to its written logical state from its initial logical state by the electrical stimulus pulse provided by said energy harvester.

Abstract: A semiconductor layout design analyzer alerts a user of areas in a semiconductor layout design that may be candidates for radiation induced inversion. The analyzer includes means for gathering information, means for identifying, and means for alerting the user. The means for gathering gathers, from the layout design, placement information for thick oxide, low-doped p-type single crystal silicon, and n-type silicon. The means for identifying identifies, in the layout design, thick oxide overlaying low-doped p-type single crystal silicon and abutting n-type silicon. The means for alerting the user alerts the user of the identified areas of thick oxide.

Abstract: Novel modifying agents contain a sharply-melting crystalline polymer ingredient, preferably a side chain crystalline (SCC) ingredient, and an active chemical ingredient. Such modifying agents, especially when in the form of particles, can be placed in contact with a matrix, will not modify the matrix below the crystalline melting point Tp, but will rapidly modify the matrix above Tp. The active chemical ingredient can react with the matrix, catalyze a reaction of the matrix, or inhibit a reaction of the matrix. Particularly useful compositions are polymer precursors which are storage-stable at low temperatures but which are rapidly converted to crosslinked resins when heated to temperatures above Tp, optionally in the presence of light.

Abstract: A ferroelectric field effect transistor (FET) has a gate, source, drain, and substrate. A negative voltage is applied to the gate. Ground potential is applied to the source, drain, and substrate. The negative voltage has a magnitude at least equal to the coercive voltage of the FET. A positive voltage is then applied to the gate. Ground potential is applied to the source and substrate. The positive voltage is no less than the coercive voltage. Either a positive voltage or a ground potential is applied to the drain to write a logic state to the FET. A voltage is applied to the gate. Ground potential is applied to the source. A positive voltage is applied to the drain. The drain current is measured and compared to a compare current. The relative size of the drain current compared to the compare current is indicative of the stored logic state in the FET.

Abstract: A ferroelectric integrated circuit memory device includes: a plurality of memory cells, each including a ferroelectric material, a plurality of conducting lines, each connected to or connectable to a selected one of the memory cells; a drive circuit for applying a predetermined voltage for a predetermined time to a selected one of the conducting lines, the predetermined voltage and time being the normal voltage and time required to perform write or read functions to the memory cell, a function selected from the group of: writing a logic state to the selected memory cell, and reading the selected memory cell; and a mode control circuit responsive to an external signal for adjusting the predetermined voltage or the predetermined time to perform an operation selected from the group consisting of: a partial read of the selected memory cell, and a partial write of the selected memory cell; and applying ferroelectric stress to the memory cell.

Abstract: Novel modifying agents contain a sharply-melting crystalline polymer ingredient, preferably a side chain crystalline (SCC) ingredient, and an active chemical ingredient. Such modifying agents, especially when in the form of particles, can be placed in contact with a matrix, will not modify the matrix below the crystalline melting point Tp, but will rapidly modify the matrix above Tp. The active chemical ingredient can react with the matrix, catalyze a reaction of the matrix, or inhibit a reaction of the matrix. Particularly useful compositions are polymer precursors which are storage-stable at low temperatures but which are rapidly converted to crosslinked resins when heated to temperatures above Tp, optionally in the presence of light.

Abstract: A ferroelectric memory includes memory cells comprising a transistor having a source/drain, a ferroelectric capacitor having a first electrode and a second electrode. A plate line is connected to each of the second electrodes. In each memory cell, the first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated nodes of a pair of memory cells at a predetermined time to essentially equalize the voltages on the nodes. The shunt may be a Schottky diode, a resistor, and a pair of back-to-back diodes, or a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.

Abstract: A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.

Abstract: A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.

Abstract: A ferroelectric integrated circuit memory includes a memory cell having a first ferroelectric capacitor, one electrode of which is connected to a first bit line through a first transistor and the other electrode of which is connected to a plate line; and a second ferroelectric capacitor, one electrode of which is connected to a second bit line through a second transistor and the other electrode of which is connected to the plate line. The plate line is parallel to the bit lines. The plate line is at 1/2 Vdd. The cell is written to by driving both bit lines either to Vdd or zero volts. The cell is read by driving one bit line to Vdd and the other to zero volts, and sensing the voltage change on the plate line. A shunt system holds the isolated node to the same voltage as the plate line when the row is not selected, thus providing a ferroelectric memory architecture that is unaffected by changes, such as aging, in the ferroelectric material, and has no disturb voltages.