Abstract: A door lock system can comprise a door lock movable between a locked state and an unlocked state. The door lock system can detect a first indication suggestive of a presence of a mobile computing device of a visitor. The door lock system can also detect a second indication suggestive of an identity of the visitor. Further, the door lock system can validate that the first indication and the second indication are associated with a known identity of the visitor.

Abstract: A door lock system can comprise a door lock movable between a locked state and an unlocked state. The door lock system can detect a first indication suggestive of a presence of a mobile computing device of a visitor. The door lock system can also detect a second indication suggestive of an identity of the visitor. Further, the door lock system can validate that the first indication and the second indication are associated with a known identity of the visitor.

Abstract: A door lock system can comprise a door lock movable between a locked state and an unlocked state. The door lock system can detect a first indication suggestive of a presence of a mobile computing device of a visitor. The door lock system can also detect a second indication suggestive of an identity of the visitor. Further, the door lock system can validate that the first indication and the second indication are associated with a known identity of the visitor.

Abstract: A dish drying rack includes a basin, a side bay pivotally connected with the basin for movement about a side bay pivot axis, and a plate rack pivotally connected with the basin for movement about a plate rack pivot axis. The basin includes a basin floor. The side bay moves between a collapsed position and an extended position. The side bay includes a side bay floor. When the side bay is in the extended position, the side bay floor is positioned with respect to the basin such that water drains from the side bay floor toward and onto the basin floor. The plate rack pivot axis is transverse to the side bay pivot axis. The plate rack is movable between an upright position and a flattened position.

Abstract: In a fiber channel network environment wherein an autonomous hub is provided with a switchable connection to another autonomous hub, an autonomous hub being an arbitrated loop with at least one port, a method is provided for maintaining switchable access between the autonomous hubs while also maintaining access fairness without degrading throughput. The method includes allowing all uncommitted ports to arbitrate together on an integrated hub, while preventing ports on those autonomous hubs which contain a port that has been committed to a loop circuit, from winning arbitration. While the established loop circuits are concurrently exchanging data, arbitration is conducted among the remaining ports which desire access to the integrated hub. Since autonomous hubs containing committed ports are effectively excluded from arbitration, the other ports on those busy hubs cannot win an arbitration and thereby prevent connection of multiple current circuits.

Abstract: In a fibre channel network environment wherein an arbitrated loop is provided a switchable connection with another arbitrated loop, a technique and corresponding apparatus are provided for controlling signal paths through the hubs stack between any two devices such that routing of a signal and interactive communication can be carried out transparently to the fibre channel network without excessive overhead, and wherein control is changed in an orderly manner such that end-to-end device connections are unaware that they are not connected to the same hub. A switched arbitrated loop (SAL) according to the invention provides the concurrent bandwidth resource of a fabric switch without the extra features which would increase design cost and operational overhead. In a specific embodiment, a switched arbitrated loop supports only 126 nodes for stations (plus one fabric port) in a single loop topology.

Abstract: In a backplane architecture for a logical stackable Ethernet repeater for an Ethernet network having a plurality of stackable repeater modules, each one of the stackable repeater modules being connectable via bus-type signal lines to one another for communicating packets via bus-type signal lines, and each one of said stackable repeater modules including a plurality of ports for connection to stations, a method is provided for communicating management information wherein a management module collects information about packets on the backplane from repeater modules, and the repeater modules transmit packet information only via bus-type signal lines. In a specific embodiment, transmitting comprises appending after each packet at each source port of each repeater module an information footer having a select number of information units, and conveying each packet with the information footer on the bus-type signal lines.

Abstract: A Class II stackable 100 Mbps Ethernet repeater architecture achievable by use of two different types of wired-OR interconnection in an Ethernet backplane, a Bus Transceiver Logic (BTL) wired-OR to selected control, data and clock lines, and a high-speed Transistor-Transistor Logic (TTL) which is wired-OR'ed together in three-level logic on a common activity signal line. The backplane has sufficiently low signal latency to permit two logical repeaters to be connected together with at least eight stackable repeater modules in each logical repeater, each repeater module having thirteen to sixteen station ports to support as many as 254 stations in a 100 Mbps environment with a diameter of 205 meters, which is up to 8.5 times greater than previously achievable.

Abstract: A digital frequency discrimination circuit includes an edge detector coupled to receive a transmission signal for producing an edge detected signal; an edge timer including a shift register clocked by the clock signal and having the edge detected signal as a data input, and a timeout determining subcircuit having a plurality of bits of the shift register coupled as edge detection inputs, for determining and providing a timeout signal indicating whether any of the edge detection inputs represents an edge detection; and a state machine circuit coupled to receive the clock signal, the edge detected signal, and the timeout signal for producing an unsquelch signal indicating whether the transmission signal meets frequency discrimination requirements.