Abstract: A circuit for use with a PC16550D UART in 16450 polling mode that will filter DR bit oscillations. The circuit latches the value of the Line Status Register during the valid data portion of a LSR register read cycle, deasserts the read strobe, delays to allow the data bus values to float, applies the latched values of the LSR to the data bus, then asserts a ready signal to the microprocessor. If the UART access is not a read cycle to the LSR, the delay time is bypassed and the UART access cycle proceeds normally.

Abstract: A circuit for use with a PC16550D UART in 16450 polling mode that will filter DR bit oscillations. The circuit latches the value of the Line Status Register during the valid data portion of a LSR register read cycle, deasserts the read strobe, delays to allow the data bus values to float, applies the latched values of the LSR to the data bus, then asserts a ready signal to the microprocessor. If the UART access is not a read cycle to the LSR, the delay time is bypassed and the UART access cycle proceeds normally.

Abstract: A car space measurement apparatus for tracking a rail vehicle position on a track is provided, which includes a wayside sensor and a supervisory processor. The wayside sensor senses multiple track parameters that are representative of the rail vehicle position. The supervisory processor receives selected track parameters and determines the rail vehicle position therefrom. Also the supervisory processor asynchronously displays a track position indication representative of the rail vehicle position. The apparatus can have an operational mode, a calibration mode, and a self -test mode. The selected track parameters are analog track phase signals. The supervisory processor can include an analog signal processor, a phase processor for determining the track position indication and a control processor for asynchronously receiving and displaying the track position indication. The asynchronous interface can be a asynchronous computer bus interface.

Abstract: A circuit for detecting and verifying a presence of a terminating device for a high speed data transmission line. The circuit contains a first cable detector which generates a first signal if a first cable is present. A second cable detector generates a second signal if a second cable is present. The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector generates an ALL-EQUIPPED signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plurality of resistor packs are present, the NON-EQUIPPED signal is generated when all of the plurality of resistor packs are absent. Finally, a verifier circuit receives the first signal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal.

Abstract: This arrangement provides for attaching test or probe leads for such instruments as a logic analyzer to a leaded chip carrier. This arrangement provides for terminating each chip carrier lead to a metallic post upon which a logic probe or other test apparatus may be mechanically attached to make electrical connection. Since leaded chip carriers have their contact leads closely spaced, this arrangement expands this distance between leads to a suitable distance for connecting test probes. In this manner, the semiconductor chip may be functionally tested as part of a circuit on a printed wiring card.