Abstract: A data processing system includes a system fabric, a system memory, a memory controller, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link to a destination host with which the source host is non-coherent. A plurality of processing units is configured to execute a logical partition and to migrate the logical partition to the destination host via the communication link. Migration of the logical partition includes migrating, via a communication link, the dataset of the logical partition executing on the source host from the system memory of the source host to a system memory of the destination host. After migrating at least a portion of the dataset, a state of the logical partition is migrated, via the communication link, from the source host to the destination host, such that the logical partition thereafter executes on the destination host.

Abstract: In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.

Abstract: In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.

Abstract: A data processing system includes a system fabric, a system memory, a memory controller, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link to a destination host with which the source host is non-coherent. A plurality of processing units is configured to execute a logical partition and to migrate the logical partition to the destination host via the communication link. Migration of the logical partition includes migrating, via a communication link, the dataset of the logical partition executing on the source host from the system memory of the source host to a system memory of the destination host. After migrating at least a portion of the dataset, a state of the logical partition is migrated, via the communication link, from the source host to the destination host, such that the logical partition thereafter executes on the destination host.

Abstract: A computing device, a non-transitory computer readable storage medium, and a method are provided for automatically recreating lost storage volumes. A volume command including volume metadata associated with a storage volume of an SCM storage device is received. The volume metadata is stored at another storage device that is less volatile than the SCM storage device. The storage volume is configured in accordance with the volume command including forwarding the volume command to an SCM device driver. A notification of a persistence loss at the SCM storage device is received subsequent to forwarding the volume command. The volume metadata is retrieved from the other storage device subsequent to receiving notification of the persistence loss. The storage volume is automatically re-configured in accordance with the volume command including submitting the retrieved volume metadata to the SCM device driver.

Abstract: An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.

Abstract: An apparatus for bypassing an invalidate search of a lookaside buffer includes a filter circuit that directs an invalidate command to a LPID/PID filter of an MMU of a processor and searches for an identifier targeted by the invalidate command. The MMU is external to cores of the processor. The apparatus includes an LPID/PID miss circuit that bypasses searching the lookaside buffer for addresses targeted by the invalidate command and returns a notification that the invalidate command did not identify the identifier targeted by the invalidate command in response to the filter circuit determining that the identifier targeted by the invalidate command is not stored in the LPID/PID filter.

Abstract: A program operating to test a computer has a limit to the number of certain components that it can utilize, less than the number of those components included in the computer. A resource allocator program receives a signal to modify allocation of resources to the programs executing in the computer. The resource allocator detects that the computer is operating in a mode for testing and selects a subset of the components not allocated to the program to swap for those presently allocated. The resource allocator can receive the signal repeatedly to complete testing the computer.

Abstract: A program operating to test a computer has a limit to the number of certain components that it can utilize, less than the number of those components included in the computer. A resource allocator program receives a signal to modify allocation of resources to the programs executing in the computer. The resource allocator detects that the computer is operating in a mode for testing and selects a subset of the components not allocated to the program to swap for those presently allocated. The resource allocator can receive the signal repeatedly to complete testing the computer.

Abstract: Prevention of “context-changing interrupts” (see definition, below) and/or “performance-affecting interventions” (see definition, below) to be made with respect to a newly-dispatched program before the relevant control registers associated with the program have been initialized. This can be especially helpful in systems where control registers are not initialized until the newly-dispatched program needs to use a facility and/or resource that requires initialization of the control registers.

Abstract: A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.

Abstract: A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.