Abstract: Techniques are disclosed for improved data routing and forwarding by exploiting the increasing number of logical cores in a computing system. In certain embodiments, a network device comprising several network interfaces and logical cores is disclosed. The network device may also include a plurality of processing nodes, wherein each processing node includes instructions for processing network packets and is associated with a logical core. Furthermore, the network device may include control logic configured to receive a network packet at an interface, select a subset of processing nodes from the plurality of processing nodes for processing the network packet, based on contents of the network packet and the interface that the network packet was received at, and schedule processing of the network packet by the subset of the processing nodes on the respective logical cores associated with each of the subset of the processing nodes.

Abstract: A backlit system comprises a base panel, a plurality of keys disposed on the base panel, a substantially planar light guide panel disposed between the base panel and the plurality of keys, at least one light source disposed on the light guide panel, and at least one light management feature disposed on the light guide panel. The at least one light management feature is configured to at least partially reflect incident light within the light guide panel.

Abstract: A program operating to test a computer has a limit to the number of certain components that it can utilize, less than the number of those components included in the computer. A resource allocator program receives a signal to modify allocation of resources to the programs executing in the computer. The resource allocator detects that the computer is operating in a mode for testing and selects a subset of the components not allocated to the program to swap for those presently allocated. The resource allocator can receive the signal repeatedly to complete testing the computer.

Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.

Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Abstract: A healthcare workflow manager may include processing circuitry configured to receive health data relating to a plurality of patients currently admitted or expected to be currently admitted to a healthcare facility and generate a plurality of patient profiles based on the health data, the plurality of patient profiles enabling management of a labor and delivery process of each of the plurality of patients, where each patient profile of the plurality of patient profiles includes a plurality of data categories relating to the labor and delivery process of each of the plurality of patients. The processing circuitry may be even further configured to transmit and cause display of the plurality of patient profiles on a user interface.

Abstract: Prevention of “context-changing interrupts” (see definition, below) and/or “performance-affecting interventions” (see definition, below) to be made with respect to a newly-dispatched program before the relevant control registers associated with the program have been initialized. This can be especially helpful in systems where control registers are not initialized until the newly-dispatched program needs to use a facility and/or resource that requires initialization of the control registers.

Abstract: The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.

Abstract: Systems, methods, and computer program products to perform an operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt, and responsive to the lightweight HDEC interrupt, initiating an asynchronous hardware operation on the shared processor prior to completion of the dispatch cycle.

Abstract: A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.

Abstract: Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

Abstract: Performing a checkpoint includes determining a checkpoint boundary of the checkpoint for a virtual machine, wherein the virtual machine has a first virtual processor, determining a scheduled hypervisor interrupt for the first virtual processor, and adjusting, by operation of one or more computer processors, the scheduled hypervisor interrupt to before or substantially at the checkpoint boundary.

Abstract: A weight applicator system includes a shaft, an applicator assembly, and a weight feed assembly. The shaft defines a length between a proximal end and a distal end configured to support a wheel-tire assembly for common rotation about a longitudinal axis of the shaft. The applicator assembly is supported by the shaft and includes a base portion disposed upon the shaft and operable to translate axially along the length of the shaft, a radial portion connected to the base portion and operable to radially move relative to the base portion between a retracted position and an extended position; and a pressure roller rotatably supported by the radial portion about an axis of rotation. The weight feed assembly is operable to feed a prescribed length of weighted material to the pressure roller.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: Method to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: A technique for improving random number generation (RNG) security for a data processing system includes a storage subsystem of a processing unit receiving a first deliver a random number (DARN) operation. The storage subsystem issues the first DARN operation with a first value, retrieved from a first base address register (BAR), on a first bus. The processing unit receives (from a first RNG unit) at least one of a first data and a first indication (that indicate whether the first RNG unit is functional) when a second value stored in a second BAR of the first RNG unit is the same as the first value. In response to the first and second values not being the same or the first RNG unit not being functional, the storage subsystem issues the first DARN operation with the first value on a second bus that is coupled to a second RNG unit.

Abstract: A push-to-talk headset can include one or more user-actuatable switches, user-actuatable adjustment devices or the like that are electrically coupled to a pulse generator circuit. Responsive to detected state transitions of the one or more user-actuatable switches, user-actuatable adjustment devices or the like, a number of signals comprising a number of pulses may be communicated to a portable electronic device communicably coupled to the push-to-talk headset. At least a first of these signals having a first number of pulses may be used to place the portable electronic device in a push-to-talk mode. At least a second of these signals having a second number of pulses may be used by the operating system to remove the portable electronic device from the push-to-talk mode.

Abstract: Performing a checkpoint includes determining a checkpoint boundary of the checkpoint for a virtual machine, wherein the virtual machine has a first virtual processor, determining a scheduled hypervisor interrupt for the first virtual processor, and adjusting, by operation of one or more computer processors, the scheduled hypervisor interrupt to before or substantially at the checkpoint boundary.