Abstract: Environmentally friendly refrigerant blends utilizing refrigerants including 2,3,3,3-tetrafluoropropene (HFO-1234yf), E-1,2-difluoroethylene (HFO-1132E), and 1,1-difluoroethane (HFC-152a). The blends have low GWP, low toxicity, and low flammability with low temperature glide for use in a hybrid, mild hybrid, plug-in hybrid, or full electric vehicles for thermal management (transferring heat from one part of the vehicle to the other) of the passenger compartment providing air conditioning (A/C) or heating to the passenger cabin.

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

Abstract: Environmentally friendly refrigerant blends utilizing refrigerants including 2,3,3,3-tetrafluoropropene (HFO-1234yf), 1,2-difluoroethylene, at least one hydrocarbon selected from the group consisting of propane, cyclopropane, propylene, isobutane, and n-butane, and optionally 1,1-difluoroethane (HFC-152a). The blends have low GWP, low toxicity, and low flammability with low temperature glide for use in a hybrid, mild hybrid, plug-in hybrid, or full electric vehicles for thermal management (transferring heat from one part of the vehicle to the other) of the passenger compartment providing air conditioning (A/C) or heating to the passenger cabin.

Abstract: An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.

Abstract: Systems and methods may determine an amount of current being drawn by a light source and determine, based on the amount of current, a type of light source. Based on the type of light source, an amount of time associated with disabling the light source may be determined. A voltage may be supplied to the light source for the amount of time.

Abstract: A system and method of modifying a binaural signal using headtracking information. The system calculates a delay, a first filter response, and a second filter response, and applies these to the left and right components of the binaural signal according to the headtracking information. The system may also apply headtracking to parametric binaural signals. In this manner, headtracking may be applied to pre-rendered binaural audio.

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: Compounds, and pharmaceutically acceptable salts thereof, useful as inhibitors of sodium channels are provided. Also provided are pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts and methods of using the compounds, pharmaceutically acceptable salts, and pharmaceutical compositions in the treatment of various disorders, including pain.

Abstract: Apparatus includes a sample holder with a cavity and a plurality of devices configured to hold a curvature of a curved substrate in a fixed configuration. Apparatus includes two prisms with a viewing apparatus of the sample holder configured to translate therebetween. Methods can include disposing the curved substrate in the sample holder, transmitting a first beam, translating the sample holder, and transmitting a second beam. Alternatively, apparatus include a light scattering-polarimetry sub-system configured to emit a first beam to impinge an end surface of coupling prism and detect at least a portion of the first beam impinging the first surface of the coupling prism. The apparatus includes an evanescent prism coupling spectroscopy sub-system configured to emit a second beam to impinge a first surface of the coupling system and detect at least a portion of the second beam impinging the second surface of the coupling prism.

Abstract: Compounds, and pharmaceutically acceptable salts thereof, useful as inhibitors of sodium channels are provided. Also provided are pharmaceutical compositions comprising the compounds or pharmaceutically acceptable salts and methods of using the compounds, pharmaceutically acceptable salts, and pharmaceutical compositions in the treatment of various disorders, including pain.

Abstract: A method and system for measuring signal loss in a fiber optic cable. The tail ends of reference and test fiber optic cables are illuminated with a diffuse light. The head end of each of the reference and test fiber optic cables are positioned in a measurement area. A core imager captures an image of the core of each head-end while it is in the measurement area. Reference and test radiant fluxes emitted from the reference and test head-ends are determined from the respective core images. The relative signal loss of the test fiber optic cable is then determined by comparing the test radiant flux to the reference radiant flux.

Abstract: Provided are methods, systems, and devices for generating semantic objects and an output based on the detection or recognition of the state of an environment that includes objects. State data, based in part on sensor output, can be received from one or more sensors that detect a state of an environment including objects. Based in part on the state data, semantic objects are generated. The semantic objects can correspond to the objects and include a set of attributes. Based in part on the set of attributes of the semantic objects, one or more operating modes, associated with the semantic objects can be determined. Based in part on the one or more operating modes, object outputs associated with the semantic objects can be generated. The object outputs can include one or more visual indications or one or more audio indications.

Abstract: A printing plate pressure adjustment system for a can decorator including a printing plate cylinder assembly having a printing plate cylinder drive shaft, and a blanket wheel. The system includes an actuator, a control system structured to control operation of the actuator to adjust a pressure between the printing plate cylinder assembly and the blanket wheel, an eccentric bushing disposed around the printing plate cylinder drive shaft, wherein rotation of the eccentric bushing causes the printing plate cylinder to move toward or away from the blanket wheel, and a drive mechanism coupled between the actuator and the eccentric bushing, wherein operation of the actuator causes the drive mechanism to rotate the eccentric bushing.

Abstract: A system predicts metadata attributes associated with documents using machine learning models. The document may represent an interaction between entities. The system trains machine learning models to predict scores indicating whether a token or a sequence of token of a document represents a metadata attribute. The metadata prediction is used to annotate the document and display to users. The system receives user feedback via the user interface and uses the user feedback to evaluate or retrain the model. The system generates training data by receiving a set of annotated documents and comparing the annotated documents against other documents to identify matching documents. The system determines when to execute the machine learning based metadata prediction based on steps of document workflow executed by the system.

Abstract: A method, system, and computer program product for determining a core-to-ferrule offset of a ferrule for a fiber optic connector. A reference ferrule is physically aligned with a core imager by positioning the reference ferrule so that edges of the reference ferrule in a plurality of profile images are aligned with fiducial markers in the images. The reference ferrule is incrementally rotated about its longitudinal center access, a core image captured at each rotational angle, and a reference core-to-ferrule offset determined based on the core images. A test ferrule is physically aligned with the core imager by positioning the test ferrule so that edges of the test ferule are aligned with the edges of the reference ferrule in a plurality of profile images. The core-to-ferrule offset of the test ferrule is then determined based on an offset between the test and reference cores in a composite core image.

Abstract: A processing device receives a request to write data to a memory device. The processing device generates a codeword based on the data. The codeword comprises the data and error correction code. The processing device generates a compressed codeword by compressing the codeword. The processing device stores the compressed codeword on a page of the memory device.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.