Patents by Inventor David A. Matthews

David A. Matthews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INFUSION SYSTEM AND COMPONENTS THEREOF
    Publication number: 20220257853
    Abstract: Certain embodiments provide multi-medicament infusion systems for preventing the cross-channeling of medicaments. The system may include one or more of an infusion pump, medicament cartridges, cartridge connectors, a multi-channel fluid conduit, and an infusion set. The infusion pump can have an inductively chargeable battery assembly that can be charged by an inductive charging pad.
    Type: Application
    Filed: March 18, 2022
    Publication date: August 18, 2022
    Inventors: David Matthew Henderson, Todd S. Ray, Michael J. Rosinko, Bryan Dale Knodel
  • Handling non-correctable errors
    Patent number: 11416334
    Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to receive a transaction from a master, the transaction directed to the first memory and comprising an address; re-calculate an error correcting code (ECC) for a line of data in the second memory associated with the address; determine that a non-correctable error is present in the line of data in the second memory based on a comparison of the re-calculated ECC and a stored ECC for the line of data; and in response to the determination that a non-correctable error is present in the line of data in the second memory, terminate the transaction without accessing the first memory.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 16, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: David Matthew Thompson, Abhijeet Ashok Chachad
  • CACHE SIZE CHANGE
    Publication number: 20220253382
    Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Inventors: Abhijeet Ashok CHACHAD, Naveen BHORIA, David Matthew THOMPSON, Neelima MURALIDHARAN
  • PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
    Publication number: 20220245069
    Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Abhijeet Ashok Chachad, Hung Ong
  • TAG UPDATE BUS FOR UPDATED COHERENCE STATE
    Publication number: 20220237122
    Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem by a transaction bus and a tag update bus. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives a message from the L1 controller over the tag update bus, including a valid signal, an address, and a coherence state. In response to the valid signal being asserted, the L2 controller identifies an entry in the shadow L1 main cache or the shadow L1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.
    Type: Application
    Filed: April 19, 2022
    Publication date: July 28, 2022
    Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON, Naveen BHORIA, Peter Michael HIPPLEHEUSER
  • GLOBAL COHERENCE OPERATIONS
    Publication number: 20220229690
    Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions.
    Type: Application
    Filed: April 5, 2022
    Publication date: July 21, 2022
    Inventors: Abhijeet Ashok CHACHAD, Naveen BHORIA, David Matthew THOMPSON, Neelima MURALIDHARAN
  • Aliased mode for cache controller
    Patent number: 11392498
    Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 19, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan
  • Caffeine inhibitors of MTHFD2 and uses thereof
    Patent number: 11370792
    Abstract: The present invention provides compounds, compositions thereof, and methods of using the same.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 28, 2022
    Assignee: Raze Therapeutics, Inc.
    Inventors: Nello Mainolfi, Mikel P. Moyer, Eddine Saiah, Cristina Lecci, Robert David Matthew Pace, Heather Tye, Julia Vile
  • OCCLUSION DETECTION IN AMBULATORY MEDICAMENT PUMPS
    Publication number: 20220184300
    Abstract: Ambulatory medicament devices that provide therapy to a subject, such as blood glucose control, are disclosed. Disclosed systems and methods can implement one or more features that improve the user experience, by modifying delivery of therapy to a subject after determining that a possible occlusion exists in a medicament delivery system, monitoring the status of an ambulatory medical device and the health condition of a subject that receives therapy from the ambulatory medical device and annunciating alarm condition when necessary, selectively muting alarm annunciations while a Do Not Disturb mode is activated, implementing various power saving modes to save power, controlling operation of the device and medicament delivery based on the user gesture controls, and controlling medicament delivery based on a condition of the ambulatory medicament device.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: David Chi-Wai Lim, Firas H. El-Khatib, Himanshu Patel, Michael J. Rosinko, David Matthew Henderson
  • Portable grilling system
    Patent number: 11357356
    Abstract: A portable grilling system comprising a grate formed of a non-flammable material; at least two support members formed of a non-flammable material and pivotally attached to the grate; at least one fuel insert support member formed of a non-flammable material and positioned below the grate; and a fuel insert comprising a base tray formed of a biodegradable material having a bottom surface and one or more sidewalls extending upwards from the bottom surface; a biodegradable and non-flammable liner positionable within the base tray; and a fuel source positionable within the liner.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 14, 2022
    Assignee: Fire & Flavor Grilling Co.
    Inventors: Davis Purcell Knox, Jeffrey Paul Broadrick, Kyle Dean Aasness, David Matthew Williams Hemming, Joseph William Pruitt
  • METHOD, APPARATUS, AND SYSTEM FOR IDENTIFYING THE HEALTH STATUS OF A PERSON
    Publication number: 20220181033
    Abstract: Provided herein is a method, apparatus, and system for identifying a health status of an individual, by using a health challenge of the individual to gather vital sign information to generate a health status of the individual. Method for identifying health status include: generating a non-persistent identifier for a user; receiving an indication of an initiation of a health challenge for the user associated with the non-persistent identifier; receiving, responsive to the health challenge, an indication of at least one vital sign of the user; determining, from the at least one vital sign, a health status of the user; and providing an indication of the health status of the user and the associated non-persistent identifier, where the health status includes a binary indication of health of the user, and where the health status is used to permit or deny a service to the user.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 9, 2022
    Applicant: THE BOEING COMPANY
    Inventors: Robert J. RENCHER, David Matthew YAGER, Roland Nelson FREEMAN, Rahul C. THAKKAR, Sumant HATTIKUDUR, Guijun WANG, David Wayne NELSON
  • CACHE COHERENCE SHARED STATE SUPPRESSION
    Publication number: 20220164287
    Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 26, 2022
    Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON, Timothy David ANDERSON, Kai CHIRCA
  • MERGING DATA FOR WRITE ALLOCATE
    Publication number: 20220164217
    Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.
    Type: Application
    Filed: December 6, 2021
    Publication date: May 26, 2022
    Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON
  • ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER
    Publication number: 20220164252
    Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Abhijeet Ashok CHACHAD, David Matthew THOMPSON, Son Hung TRAN
  • Electronic device
    Patent number: D953322
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 31, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Jesse Wheeler Moore, Giles David Matthew McWilliam
  • Electronic device
    Patent number: D954681
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: June 14, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Edward James Paterson, Giles David Matthew McWilliam
  • Earbud
    Patent number: D954684
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Emmanuel Laffon de Mazieres, Giles David Matthew McWilliam
  • Electronic device
    Patent number: D954749
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 14, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Jesse Wheeler Moore, Giles David Matthew McWilliam
  • Earbuds case
    Patent number: D959143
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: August 2, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Emmanuel Laffon de Mazieres, Giles David Matthew McWilliam
  • Electronic device
    Patent number: D959408
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 2, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Sun Joo Han, Giles David Matthew McWilliam