Patents by Inventor David A. Milley

David A. Milley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adjustable test pattern results latency
    Patent number: 7788564
    Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: August 31, 2010
    Assignee: Teradyne, Inc.
    Inventors: Michael F. McGoldrick, William T. Borroz, Stephen K. Eng, David A. Milley
  • Adjustable test pattern results latency
    Publication number: 20090100303
    Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.
    Type: Application
    Filed: November 21, 2007
    Publication date: April 16, 2009
    Applicant: Teradyne, Inc.
    Inventors: Michael F. McGoldrick, William T. Borroz, Stephen K. Eng, David A. Milley
  • Systems and methods for the emulation of TDM circuits over a real-time scheduled packet network
    Patent number: 7239638
    Abstract: A system and method to emulate any TDM circuit on a Real-Time Scheduled Packet Network. The TDM circuit can be any serial or parallel bit stream, of any bit rate, and can either be synchronized to the Real-Time Scheduled Packet Network, or can be asynchronous to the network. The present system and method determines the requisite descriptors of a scheduled IP itinerary for any emulated TDM circuit.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: July 3, 2007
    Assignee: Avaya Technology, LLC
    Inventors: Dale J. Wisler, Howard C. Reith, David A. Milley
  • Systems and methods for the emulation of TDM circuits over a real-time scheduled packet network
    Publication number: 20030219012
    Abstract: A system and method to emulate any TDM circuit on a Real-Time Scheduled Packet Network. The TDM circuit can be any serial or parallel bit stream, of any bit rate, and can either be synchronized to the Real-Time Scheduled Packet Network, or can be asynchronous to the network. The present system and method determines the requisite descriptors of a scheduled IP itinerary for any emulated TDM circuit.
    Type: Application
    Filed: March 7, 2003
    Publication date: November 27, 2003
    Inventors: Dale J. Wisler, Howard C. Reith, David A. Milley