Abstract: In a switch fabric environment, which includes a buffer, packet data of different class-types from different sources is received, stored in the buffer, processed and outputted to its intended destination. As the buffer fills up, transmission from some of the data sources is stopped to avoid dropping of packets. To avoid packet loss, when the occupancy of the buffer reaches a first threshold value, further transmission of a first-class type of data is precluded from the particular source of that data then being received, while transmission from other sources of that same first-class type of data is not precluded from these other data sources until first-class type of data from such other sources is also received. Further, data of a second-class type is not precluded from being transmitted as long as the amount of data stored in the buffer remains below a second threshold, which is greater than the first threshold.

Abstract: The current mode bus driver which is disclosed couples input digital signals to a bus which is normally biased with a voltage difference representing one binary type. The current mode bus driver responds to input digital signals of the other binary type by connecting a current source to one lead of the bus and a current sink to the other lead of the bus, thereby driving the bus to a voltage difference which represents the other binary type. In response to input digital signals of the first-mentioned binary type, the bus driver isolates the current source and current sink from the bus and connects the current source directly to the current sink. The selective switching is performed by n-channel MOSFETs which are driven by the input digital signals through unique buffer driver circuits employing a CMOS inverter, an n-channel MOSFET and an NPN transistor. A combination of MOSFETs and NPN transistors provide a current source and sink that permit operation of the bus at very low voltage levels.

Abstract: A differential voltage bus system is disclosed wherein the two leads of the bus are biased by the termination networks with a predetermined voltage difference representing a digital signal of one binary type. The bus driver in each bus master connects a current source to one of the two bus leads and a current sink to the other of the two bus leads in response to an input digital signal of the other binary type thereby changing the voltage difference on the bus to represent the other binary type. In response to an input digital signal of the first-mentioned binary type, the bus driver isolates the current source and sink from the bus and connects them together in order to decrease the detrimental effect of transients. The selective switching in the bus driver is performed by MOSFET switches which are driven by buffer driver circuits each of which uses a combination of MOSFETs and an NPN transistor to drive its respective MOSFET switch with a high peak current thereby enabling rapid switching.