Abstract: There is provided a parity check encoder (100) comprising a data memory (PPDM) configured for storing input data, a calculation/parity result data store (CPRDS), and a selector/serializer (SS). The CPRDS (104,106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SS (108) is coupled to the PPDM and CPRDS. The SS is configured to generate an encoded output sequence using the input data and parity bits. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix. A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).

Abstract: There is provided a parity check encoder (100) comprising a data memory (PROM) configured for storing input data, a calculation/parity result storage means (CPRSM), and a selector/serializer means (SSM). The CPRSM (104, 106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input data and information contained in a parity check matrix H. The SSM (108) is coupled to the PPDM and CPRSM. The SSM is configured to generate an encoded output sequence using the input data and parity bile. The matrix H is formed of a plurality of sub-matrices. Each sub-matrix of the sub-matrices is an all zero (0) matrix, an identity matrix, or a circular right shifted version of the identity matrix, A portion B of the matrix H includes a plurality of rows having two (2) ones (1), except for a first row which includes a single one (1).

Abstract: A method of detecting and correcting bit errors in a digitally encoded data stream includes correlating a received bit transition in the data stream with a multitude of possible bit transitions to generate corresponding correlated bit transition values. A bit transition decision corresponding to a greatest correlated bit transition value is then generated for the received bit transition. Consecutive bit transition decisions generated for the data stream are compared to identify bit transition decision errors. Respective bit transition decisions are examined to determine if each decision is consistent with a prior adjacent bit transition decision in the data stream. If a bit transition decision error is identified, then the next greatest correlated bit transition decision is substituted for the bit transition decision in error.

Abstract: A method for determining a location of a digital radio transmitter includes detecting, by at least three spatially separated receivers, a digitally encoded radio signal, having a known pattern of bit transitions, radiated from the transmitter. Once detected, a time of arrival of the bit transitions at each of the receivers is determined. Then, an indication of the time of arrival at each respective receiver for the bit transitions is transmitted from each of the receivers to a central processor. At the central processor, time of arrival differences of common bit transitions among the receivers are determined. Based on the time of arrival differences, the central processor may calculate the location of the transmitter.

Abstract: A method for determining a location of a digital radio transmitter includes detecting, by at least three spatially separated receivers, a digitally encoded radio signal, having a known pattern of bit transitions, radiated from the transmitter. Once detected, a time of arrival of the bit transitions at each of the receivers is determined. Then, an indication of the time of arrival at each respective receiver for the bit transitions is transmitted from each of the receivers to a central processor. At the central processor, time of arrival differences of common bit transitions among the receivers are determined. Based on the time of arrival differences, the central processor may calculate the location of the transmitter.

Abstract: A method of detecting and correcting bit errors in a digitally encoded data stream includes correlating a received bit transition in the data stream with a multitude of possible bit transitions to generate corresponding correlated bit transition values. A bit transition decision corresponding to a greatest correlated bit transition value is then generated for the received bit transition. Consecutive bit transition decisions generated for the data stream are compared to identify bit transition decision errors. Respective bit transition decisions are examined to determine if each decision is consistent with a prior adjacent bit transition decision in the data stream. If a bit transition decision error is identified, then the next greatest correlated bit transition decision is substituted for the bit transition decision in error.

Abstract: A method and system generates a modulated chirp signal in accordance with the present invention. A phase-locked loop output signal is generated, together with a sampled feedback signal from a voltage controlled oscillator. The sampled feedback signal is received within a quadrature I/Q phase modulator. I/Q quadrature signals are generated from an I/Q generator circuit to the quadrature I/Q phase modulator to produce a desired modulation of a sampled feedback signal as a string of +/−90 degree phase shifts to create a desired offset at the voltage controlled oscillator. The I/Q quadrature signals are chirp modulated and the resultant phase-locked loop output signal is chirp modulated by the chirp signal that comprises a sequence of chirps having a reference chirp followed by a plurality of data chirps.

Abstract: A correlator includes a circuit for serially receiving in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels and converting the data to blocks of n bit parallel I and n bit parallel Q signal data. At least one programmable read only memory (PROM) stores I and Q reference data. The memory receives and stores within each respective parallel I and Q signal channel a current block of n bit parallel I and n bit parallel Q signal data and the immediately previous received blocks of n bit parallel I and n bit parallel Q signal data. A data bus receives the n bit parallel I and Q reference data and the n bit parallel I and Q signal data. The n bit parallel I and Q reference data are correlated with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce a correlated I component signal output and a correlated Q component signal output.

Abstract: A correlator and method of correlating include a circuit that serially receives in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels at one input bit time periods and converts the data into blocks of n bit parallel I and n bit parallel Q signal data. A data bus receives the signal and reference data. A multiplexer is positioned in each of the n parallel paths extending from the data bus and receives the n bit parallel I and Q reference data and a one bit shifted version of the respective n bit parallel I and Q signal data from the adjacent previous path. Each multiplexer includes I and Q summed outputs based on the value of I and Q reference data on a bit-by-bit basis. An n bit Wallace Tree Adder is connected to each of the I and Q summed outputs for each multiplexer within each of the n parallel paths and computes a count based on the number of bits that are set out of n bits to form partial correlation products.

Abstract: A correlator is disclosed and includes a data bus for receiving blocks of n bit parallel in phase (I) and n bit parallel quadrature (Q) signal data and n bit parallel I and Q reference data from respective I and Q signal channels and I and Q reference channels. The I and Q reference data are correlated with a one bit shifted version of the respective n bit parallel I and Q signal data from an adjacent previous path to produce an I component signal output and Q component signal output along each of the individual n parallel paths. An output bus receives I and Q component signal outputs from the n parallel paths one at a time at one bit input time periods such that there is one correlation product output for every I and Q parallel n bits. A cascade adder circuit comprises at least one adder connected to the output bus and receives the I and Q component signal outputs from the output bus and delayed I and Q component signal outputs from another correlator.

Abstract: In a spread spectrum communications system employing cyclic code shift keying as its primary modulation, the transmission waveform is spread for transmission security by modulo-2 adding a pseudo-noise sequence to the CCSK data symbols prior to phase modulating onto a carrier signal for transmission. If the transmission modulation is minimum shift keying (MSK) the two components of the data stream are applied to the carrier with a differential encoding step implicit in the modulation scheme. This differential encoding characteristic makes stripping of the PN spread function prior to CCSK demodulation difficult at the receiving end. In order to demodulate this waveform in an optimum manner, an array correlator, the adjacent correlator stages of which have one chip relative time displacements of their CCSK reference waveform, is employed. In effect the array correlator becomes a parallel array of matched filters matched to each cyclic shift of the incoming waveform.