Patents by Inventor David A. Plaisted

David A. Plaisted has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for design verification of hardware and non-hardware systems
    Patent number: 6131078
    Abstract: A computer implemented method for verifying that a circuit or other system satisfies its specifications, is based on creating a first Boolean formula G representative of the system and its specification and through a series of steps creating a second formula G' having a known logical relationship to G and using the second formula G' to determine whether the system satisfies its specification.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: October 10, 2000
    Inventor: David A. Plaisted