Patents by Inventor David A. Podsiadlo
David A. Podsiadlo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886228Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.Type: GrantFiled: June 22, 2021Date of Patent: January 30, 2024Assignee: pSemi CorporationInventors: Poojan Wagh, David A. Podsiadlo
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Publication number: 20220405227Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.Type: ApplicationFiled: June 22, 2021Publication date: December 22, 2022Inventors: Poojan Wagh, David A. Podsiadlo
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Publication number: 20070136528Abstract: Methods and apparatus for adding an autonomous controller to an existing architecture such as by way of example, portable devices such as cell phones, MP3 players, and digital cameras. A circuit interposed between the memory card and the system controller of the device is controllable to couple the memory card to the system controller, or to couple the memory card to a high speed I/O controller on the circuit. When the memory card is coupled to the high speed I/O controller on the circuit, the circuit provides signals to the system controller indicative of a memory card removal event. In systems having an I/O connection such as a USB connection, the circuit also disconnects that connection from the system controller, provides signals to the system control indicative of a USB disconnect and connects the I/O connection to the memory card through a high speed data transfer unit to provide a higher speed I/O capability. Various features and capabilities are disclosed.Type: ApplicationFiled: May 9, 2006Publication date: June 14, 2007Inventors: Lane Hauck, Kenneth Helfrich, David Podsiadlo
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Patent number: 7185135Abstract: A USB to PCI bridge preferably includes a USB interface, a PCI interface, and an on-board processor configured to manage data flow between the interfaces. Firmware is preferably provided and configured to translate signals between the USB and PCI interfaces. The bridge can also include an internal memory configured to store instructions and data. A PCI central resource can be provided to enable hosting of a PCI subsystem. In a preferred embodiment, a plurality of PCI targets can be connected to a USB port through the bridge.Type: GrantFiled: July 12, 2002Date of Patent: February 27, 2007Assignee: Cypress Semiconductor CorporationInventors: Randall Don Briggs, David A. Podsiadlo
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Patent number: 6708244Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.Type: GrantFiled: July 22, 1999Date of Patent: March 16, 2004Assignee: Cypress Semiconductor Corp.Inventors: B. David Black, Steven P. Larky, Leah S. Clark, David A. Podsiadlo
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Publication number: 20030046475Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.Type: ApplicationFiled: July 22, 1999Publication date: March 6, 2003Inventors: B. DAVID BLACK, STEVEN P. LARKY, LEAH S. CLARK, DAVID A. PODSIADLO
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Patent number: D624762Type: GrantFiled: November 17, 2009Date of Patent: October 5, 2010Assignee: Gus Design Group, Inc.Inventor: David Podsiadlo
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Patent number: D714567Type: GrantFiled: March 11, 2014Date of Patent: October 7, 2014Assignee: Gus Design Group Inc.Inventors: David Podsiadlo, Joran Van Lange
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Patent number: D718069Type: GrantFiled: March 11, 2014Date of Patent: November 25, 2014Assignee: Gus Design Group Inc.Inventors: Nicole Marion, David Podsiadlo
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Patent number: D726436Type: GrantFiled: March 12, 2014Date of Patent: April 14, 2015Assignee: Gus Design Group Inc.Inventors: David Podsiadlo, Joran Van Lange
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Patent number: D728956Type: GrantFiled: March 11, 2014Date of Patent: May 12, 2015Assignee: Gus Design Group Inc.Inventors: Joran Van Lange, David Podsiadlo
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Patent number: D730076Type: GrantFiled: September 11, 2014Date of Patent: May 26, 2015Assignee: Gus Design Group Inc.Inventors: Joran Van Lange, David Podsiadlo
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Patent number: D731198Type: GrantFiled: September 9, 2014Date of Patent: June 9, 2015Assignee: Gus Design Group Inc.Inventor: David Podsiadlo
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Patent number: D732302Type: GrantFiled: March 12, 2014Date of Patent: June 23, 2015Assignee: Gus Design Group Inc.Inventors: Joran Van Lange, David Podsiadlo
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Patent number: D732851Type: GrantFiled: March 12, 2014Date of Patent: June 30, 2015Assignee: Gus Design Group Inc.Inventors: Joran Van Lange, David Podsiadlo
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Patent number: D739671Type: GrantFiled: March 11, 2014Date of Patent: September 29, 2015Assignee: Gus Design Group Inc.Inventors: Devin Schaffner, Joran Van Lange, David Podsiadlo
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Patent number: D762994Type: GrantFiled: September 8, 2015Date of Patent: August 9, 2016Assignee: GUS DESIGN GROUP INC.Inventor: David Podsiadlo
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Patent number: D785963Type: GrantFiled: August 25, 2015Date of Patent: May 9, 2017Assignee: GUS DESIGN GROUP INC.Inventors: David Podsiadlo, Joran Van Lange