Abstract: A power restoration system comprising a feeder, a plurality of power sources available to provide power to the feeder, a plurality of normally closed reclosing devices electrically coupled along the feeder, at least one normally open recloser electrically coupled to the feeder, and a plurality of normally closed switches electrically coupled along the feeder between each adjacent pairs of normally closed reclosing devices. Each switch is assigned a position code having a value for each of the plurality of power sources that determines when the switch will open in response to the fault current and which power source the switch is currently receiving power from, where timing control between the reclosing devices and the switches allows the switch to be selectively opened to isolate the fault within a single feeder section between each pair of adjacent switches or between each switch and a reclosing device.

Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

Abstract: Aspects of the present disclosure are related unmanned aerial vehicles tethered to ground stations with an expendable airborne fiber-optic link. The tethers may be fiber-optic cables that can be used as a communications conduit between a ground station and a UAV for providing vehicle positioning/control information to the UAV as well as transmitting a large amount of information/data to the UAV. As the information being transmitted between to the UAV the ground station is critical, fiber-optic cables provide the bandwidth and transmission capabilities required with the added benefit of electromagnetic interference (EMI) and radio-frequency interference (RFI) immunity, making this an ideal solution for these applications.

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

Abstract: Systems, device and techniques are disclosed for dynamically retrieving and monitoring geo-fence activity. A meta geo-fence may be identified based on a user device geolocation. The meta geo-fence having a radius that is dynamically generated to include previously defined geo-fences within or touching the meta geo-fence. User device geolocation may be monitored in relation to the defined geo-fences included in the radius of the meta geo-fence. A communication may be sent to the user device when the user device reports that the user device has entered or exited one of the previously defined geo-fences within or touching the radius of the meta geo-fence.

Abstract: A control system and method for sectionalizing switches and pulse-testing interrupter/reclosers in a distribution grid feeder which enables fault location, isolation and service restoration without requiring an external communications infrastructure to pass information between the switches. The method includes switches entering an armed state when they experience a high fault current during an initial fault event. Then, when the interrupter/recloser runs its test pulse sequence, any armed switch counts all test pulses as fault pulses, while non-armed switches count the test pulses as load pulses. Switches open to isolate the fault based on threshold values of fault pulse count and load pulse count. When an initially active interrupter/recloser completes its test pulse sequence, another interrupter/recloser begins its sequence, and all switches reconfigure their threshold values based on the new interrupter/recloser.

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

Abstract: A collar includes a first portion and a second portion. The first portion includes a first material strip having a first end and an opposing second end, a first connector coupled to the first end, and a second connector coupled to the opposing second end. The second portion includes a second material strip having a third end and an opposing fourth end, a third connector coupled to the third end, and a fourth connector coupled to the opposing fourth end. The first connector is configured to selectively engage with the third connector and the second connector is configured to selectively engage with the fourth connector to facilitate selectively coupling the first portion and the second portion together.

Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

Abstract: Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.

Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

Abstract: Embodiments relate to improving the biasing of active electronic components such as, for example, sense amplifiers. Embodiments include an adjustable bias signal generator that receives a reference signal as an input and generates a corresponding bias signal as an output. The adjustable bias signal generator may comprise a voltage driver and capacitor divider circuitry. In some embodiments, the capacitor divider circuitry is configurable by selecting specific capacitor dividers using a digital code. In other embodiments, the voltage driver is adjustable by applying different trim settings to tune the output of the voltage driver. The voltage driver may be temperature compensated by multiplexing different trim settings that correspond to different temperatures.

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.

Abstract: Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die may further include a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit may be located under the footprint of the array and the second ECC circuit may be located outside the footprint of the array.

Abstract: Systems, device and techniques are disclosed for dynamically retrieving and monitoring geo-fence activity. A meta geo-fence may be identified based on a user device geolocation. The meta geo-fence having a radius that is dynamically generated to include previously defined geo-fences within or touching the meta geo-fence. User device geolocation may be monitored in relation to the defined geo-fences included in the radius of the meta geo-fence. A communication may be sent to the user device when the user device reports that the user device has entered or exited one of the previously defined geo-fences within or touching the radius of the meta geo-fence.

Abstract: Some instances of a memory device include a memory die having an array of memory cells including a plurality of banks. In some cases, the memory die further includes a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. In some examples, the memory die further includes a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit is located under the footprint of the array and the second ECC circuit is located outside the footprint of the array.

Abstract: A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

Abstract: This invention discloses a design a capillary column for use with electrochemically modulated liquid chromatography (EMLC). The capillary design, which results in a marked reduction in the flow of current through the column, enables the use of a two-electrode column construction that overcomes the mechanical and electrical shortfalls of the conventional standard bore design.