Patents by Inventor David A. Pruitt

David A. Pruitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11272618
    Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 8, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: John David Brazzle, Frederick E. Beville, David A. Pruitt
  • Publication number: 20190141834
    Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module. A method of making a component-on-package circuit may include attaching a component for an electrical circuit to a circuit module. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component after the attachment both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides a spring-like cushioning of force applied to the component in the direction of the circuit module.
    Type: Application
    Filed: April 11, 2017
    Publication date: May 9, 2019
    Inventors: John David Brazzle, Frederick E. Beville, David A. Pruitt
  • Publication number: 20170311447
    Abstract: A component-on-package circuit may include a component for an electrical circuit and a circuit module attached to the component. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides spring-like cushioning of force applied to the component in the direction of the circuit module. A method of making a component-on-package circuit may include attaching a component for an electrical circuit to a circuit module. The circuit module may have circuitry and at least one leadframe which connects the circuitry to the component after the attachment both electrically and thermally. The leadframe may have a high degree of both electrical and thermal conductivity and a non-planar shape that provides a spring-like cushioning of force applied to the component in the direction of the circuit module.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 26, 2017
    Inventors: John David BRAZZLE, Frederick E. BEVILLE, David A. PRUITT
  • Publication number: 20160035645
    Abstract: A flipchip package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the flipchip package.
    Type: Application
    Filed: February 24, 2015
    Publication date: February 4, 2016
    Inventors: Edward William Olsen, David A. Pruitt, Gregory S. Peck, Leonard Shtargot
  • Patent number: 8163643
    Abstract: A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: April 24, 2012
    Assignee: Linear Technology Corporation
    Inventors: Maurice O. Othieno, Ramaswamy Ranganathan, Frederick E. Beville, David A. Pruitt, William D. Griffitts
  • Patent number: 8076181
    Abstract: A packaging technique is described for QFNs, DFN, and other surface mount packages that allows the sides of leads to be plated with a wettable metal prior to the lead frames being singulated from the lead frame sheet. The leads of the lead frames in the sheet are shorted together and to the body of the lead frame sheet by a sacrificial interconnect structure. Chips are mounted to the lead frames and encapsulated, leaving the bottoms of the leads exposed. The lead frame sheet is then sawed along boundaries of the lead frames but not sawed through the interconnect structure. The sawing exposes at least a portion of the sides of the leads. The leads are then electroplated while the leads are biased with a bias voltage via the interconnect structure. After the plating, the lead frame sheet is sawed completely thorough the interconnect structure to singulate the lead frames and prevent the interconnect structure from shorting the leads together.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: December 13, 2011
    Assignee: Linear Technology Corporation
    Inventors: David A. Pruitt, Lothar Maier
  • Patent number: 6703692
    Abstract: A leadframe is disclosed. The leadframe comprises a frame characterized by a substantially rectangular outline, a die paddle with a receiving surface, and a plurality of support members that connect the frame to the die paddle. The leadframe further comprises a plurality of leads connected to the frame, that will eventually serve to electrically connect an integrated circuit mounted on the die paddle to an external electrical device. The die paddle lies in a lower horizontal plane. A plurality of support members connect the frame with the die paddle. As projected on to a vertical plane that is perpendicular to the side of the frame to which a support member is attached, the offset angle between the support member and a vertical axis is less than 45 degrees.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: March 9, 2004
    Assignee: Linear Technology Corp.
    Inventor: David A. Pruitt
  • Patent number: 5518684
    Abstract: A lead frame for use in an integrated circuit package is herein disclosed wherein the lead frame is produced by molding an electrically conductive material into a desired lead frame shape. There is also disclosed several possible arrangements for a lead frame produced using the molding method including, protrusions on the lead frame adapted to provide a mechanical connection to the integrated circuit package, a heat sink molded as an integral part of the lead frame with heat dissipating characteristics specific to the application in which the lead frame will be used, and an arrangement which provides a heat conducting portion adapted to thermally connect a component attached to the lead frame to an external heat sink.
    Type: Grant
    Filed: May 10, 1995
    Date of Patent: May 21, 1996
    Assignee: National Semiconductor Corporation
    Inventor: David A. Pruitt