Abstract: The present disclosure provides scalable nanotube fabrics and methods for controlling or otherwise adjusting the nanotube length distribution of a nanotube application solution in order to realize scalable nanotube fabrics. In one aspect of the present disclosure, one or more filtering operations are used to remove relatively long nanotube elements from a nanotube solution until nanotube length distribution of the nanotube solution conforms to a preselected or desired nanotube length distribution profile. In another aspect of the present disclosure, a sono-chemical cutting process is used to break up relatively long nanotube elements within a nanotube application solution into relatively short nanotube elements to realize a pre-selected or desired nanotube length distribution profile.

Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

Abstract: A method for arranging nanotube elements within nanotube fabric layers and films is disclosed. A directional force is applied over a nanotube fabric layer to render the fabric layer into an ordered network of nanotube elements. That is, a network of nanotube elements drawn together along their sidewalls and substantially oriented in a uniform direction. In some embodiments this directional force is applied by rolling a cylindrical element over the fabric layer. In other embodiments this directional force is applied by passing a rubbing material over the surface of a nanotube fabric layer. In other embodiments this directional force is applied by running a polishing material over the nanotube fabric layer for a predetermined time. Exemplary rolling, rubbing, and polishing apparatuses are also disclosed.

Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.

Abstract: Disclosed herein include systems, devices, computer readable media, and methods for subsampling flow cytometric event data. First and second flow cytometric event data can be transformed into a lower-dimensional space, associated with a plurality of bins, and assigned to a first bin and a second bin. Subsampled flow cytometric event data comprising the first flow cytometric event data can be generated. The subsampled flow cytometric event data can comprise the second flow cytometric event data if the first bin and the second bin are different. The subsampled flow cytometric event data may not comprise the second flow cytometric event data if the first bin and the second bin are identical.

Abstract: Disclosed herein include systems, devices, computer readable media, and methods for subsampling flow cytometric event data. First and second flow cytometric event data can be transformed into a lower-dimensional space, associated with a plurality of bins, and assigned to a first bin and a second bin. Subsampled flow cytometric event data comprising the first flow cytometric event data can be generated. The subsampled flow cytometric event data can comprise the second flow cytometric event data if the first bin and the second bin are different. The subsampled flow cytometric event data may not comprise the second flow cytometric event data if the first bin and the second bin are identical.

Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

Abstract: A method includes, for each data value in a set of one or more data values, determining a boundary between a high order portion of the data value and a low order portion of the data value, storing the low order portion at a first memory location utilizing a low data fidelity storage scheme, and storing the high order portion at a second memory location utilizing a high data fidelity storage scheme for recording data at a higher data fidelity than the low data fidelity storage scheme.

Abstract: Methods for characterizing a nanotube formulation with respect to one or more particular ionic species are disclosed. Within the methods of the present disclosure, this characterization provides control over the surface roughness (or smoothness) and the degree of rafting within a nanotube fabric formed from such a nanotube formulation. In one aspect, the present disclosure provides a nanotube formulation roughness curve (and methods for generating such a curve) that can be used to select a utilizable range of ionic species concentration levels that will provide a nanotube fabric with a desired surface roughness (or smoothness) and degree of rafting. In some aspects of the present disclosure, such a nanotube formulation roughness curve can be used adjust nanotube formulation prior to a nanotube formulation deposition process to provide nanotube fabrics that are relatively smooth with a low degree of rafting.

Abstract: Aspects of the present disclosure include methods for processing and displaying multi-channel spectral histograms. Methods according to certain embodiments include obtaining a histogram of cytometric data for a sample, wherein the cytometric data comprises measurements from particles irradiated in the sample flowing in a flow stream, generating the representation of the histogram by encoding the histogram, the encoding comprising: assigning a color to each histogram value in the representation of the histogram, and duplicating each color corresponding to each histogram value in the representation of the histogram a predetermined number of times, and using the representation of the histogram for displaying the histogram. Systems for practicing the subject methods are also provided. Non-transitory computer readable storage mediums are also described.

Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

Abstract: Aspects of the present disclosure include methods for determining baseline noise of a photodetector (e.g., in a light detection system of a particle analyzer). Methods according to certain embodiments include irradiating a sample having particles in a flow stream, detecting light with the photodetector from the irradiated flow stream, generating data signals from the detected light and calculating a moving average mean squared error of the generated data signals to determine the baseline of the photodetector. Systems (e.g., particle analyzers) having a light source and a light detection system that includes a photodetector for practicing the subject methods are also described. Integrated circuits and non-transitory computer readable storage medium are also provided.

Abstract: An electronic device including a neural network processor and a presorter is described. The presorter determines a sorted order to be used by the neural network processor for processing a set of instances of input data through the neural network, the determining including rearranging an initial order of some or all of the instances of input data so that instances of input data having specified similarities among the some or all of the instances of input data are located nearer to one another in the sorted order. The presorter provides, to the neural network processor, the sorted order to be used for controlling an order in which instances of input data from among the set of instances of input data are processed through the neural network. A controller in the electronic device adjusts operation of the presorter based on efficiencies of the presorter and the neural network processor.

Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls a refresh operation so that a data refresh does not occur for the clean data only banks or the refresh rate is reduced for the clean data only banks. Partitions that store dirty data can also store clean data; however, other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

Abstract: A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. The controller transmits, to the addressable elements via the network, a routing table indicating the variable length addresses assigned to the addressable elements. Routers or addressable elements receive the routing table and route one or more packets over the network to an addressable element using variable length addresses included in a header of the one or more packets.

Abstract: The present disclosure provides methods for stabilizing a colloidal dispersion during transport for low defect tolerance applications. The methods involve eliminating fluid interfaces within a dispersion, storing the dispersion in an environment of inert gas, and degassing the dispersion. Several bottle closure devices are described which may be ideal for use with these methods, being able to seal a container filled with a dispersion, permit the removal of headspace and rapidly empty the contained dispersion. In one aspect, the device includes a vented cap and semi-permeable membrane, which allows the passage of gas into and out of the container, and a dispenser nozzle integrated with the device to allow a stored dispersion to be dispensed without removing the device from the container. In another aspect, the bottle closure device includes an attachment point for a removable downtube and dispenser nozzle.