Patents by Inventor David A. Seberger

David A. Seberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6195676
    Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
    Type: Grant
    Filed: January 11, 1993
    Date of Patent: February 27, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli
  • Patent number: 6018799
    Abstract: Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: January 25, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: David R. Wallace, David M. Cox, Serguei V. Morosov, David A. Seberger, Serguei L. Wenitsky
  • Patent number: 5193192
    Abstract: A parser for parsing computer programs in a compiler has parsing tables arranged as linear vectors. In a reduction portion of the parser, a production table and a lookahead set table have paired entries at identical address offsets such that a one-to-one relationship exists between each lookahead set in the lookahead set table and the representation of the lookahead set in the lookahead set table. In a read transition portion of the parser, an entrance symbol table has entries paired with transition state representations and each pair being at an identical address offset in the respective tables. For a reduction or read transition operation, the lookahead set table or the entrance symbol table is scanned to find the appropriate entry. Once the appropriate entry is found, the production table or the transition state table is addressed using the offset of the appropriate entry found during the scanning process.
    Type: Grant
    Filed: August 23, 1990
    Date of Patent: March 9, 1993
    Assignee: Supercomputer Systems Limited Partnership
    Inventor: David A. Seberger
  • Patent number: 5179702
    Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: January 12, 1993
    Assignee: Supercomputer Systems Limited Partnership
    Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli
  • Patent number: 5175856
    Abstract: A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.
    Type: Grant
    Filed: August 23, 1990
    Date of Patent: December 29, 1992
    Assignee: Supercomputer Systems Limited Partnership
    Inventors: Don A. Van Dyke, Timothy J. Cramer, James C. Rasbold, Kelly T. O'Hair, David M. Cox, David A. Seberger, Linda J. O'Gara, Jon A. Masamitsu, Robert E. Strout, II, Ashok Chandramouli