Abstract: A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the “compressive” DMA.

Abstract: In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.

Abstract: A microcontroller architecture and an associated method are presented which provide for testing of an “on-chip” memory unit. The microcontroller includes a microcontroller core, the memory unit, a set of input/output (I/O) pads, and an input/output (I/O) pad interface unit, all formed upon a single monolithic semiconductor substrate. The microcontroller core executes instructions and generates data. The memory unit is coupled to the microcontroller core and stores data. The memory unit may include a common static random access memory (SRAM) device having multiple memory cells with load devices permitting static operation. A data latch within the memory unit samples retrieved data and provides the retrieved data to the microcontroller core. The data latch is responsive to a data latch control (DLC) signal produced by the I/O pad interface unit. The I/O pad interface unit receives a signal from one or more members of the set of I/O pads and generates the DLC signal in response to the signal.

Abstract: A processor-oriented device provides a watchdog timer having a test mode programmable reset. When the device is placed in a test mode by pulling a test mode hardware pin during a reset of the timer and then an appropriate write key is provided to the timer, a watchdog timer reset count is writeable, allowing for a programmable duration for a watchdog timer reset. The watchdog timer reset count may be a reset duration value maintained by a watchdog timer reset counter. Based on both a test mode signal from watchdog timer test mode enable logic and a write key, watchdog timer reset write enable logic enables writes to the watchdog timer reset count.

Abstract: A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that polls buffer descriptors when in idle mode. This polling is to determine whether the software has set up a buffer or group of buffers transmission and transfer ownership of those buffers to the DMA unit. To reduce interrupt latency and bandwidth occupation, the polling of these buffer descriptor ownership flags is staggered for the DMA channels. For example, if eight DMA channels are implemented, the polling of their buffer descriptors can be distributed throughout a 1.28 millisecond polling interval.

Abstract: A processing unit having a CPU core, an integrated RAM and a test unit, which may be implemented in either a test unit, which may be implemented in either hardware or software. A built-in self-test of the RAM is designed to run concurrently with the functional vectors used to test the CPU core. Once the core tests have been activated, a control register may be written to by which will activate the built-in self-test. Thus, the BIST and core testing may overlap to minimize test time.