Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: A read buffering system and method employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: A memory system has a stream buffer with several performance-enhancing features. Two distinct sets of latches receive data from the memory array. One set feeds the stream buffer, while the other holds memory data that is destined for a system bus. The dual-latch configuration allows stream buffer fills to proceed even if system bus stalls prevent the memory data latch from being timely emptied. The memory controller prefetches a number of data blocks depending on the interleave factor of the memory system, as well as in response to control information from the CPU that can override the interleave-based number in some system configurations. The stream buffer employs a history buffer containing the addresses of recently-read memory locations in order to declare a new stream. The addresses of memory reads are normally entered into the history buffer on a round-robin basis.

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: The operation of a stream buffer varies depending on whether a normal operation mode or a test mode is selected. In the normal operation mode, the stream buffer is read from only when the data requested by a CPU read has been determined to reside there, and the stream buffer location read from is the location determined to contain the requested data. This determination is made by comparing the address of the read request with addresses of the data stored in the stream buffer. Also, the stream buffer is written with memory data in response to a read that misses the stream buffer, and the location written to is one that has been allocated to receive the incoming memory data. Two different buffer allocation methods are shown, first-in-first-out (FIFO) and least-recently-used (LRU).

Abstract: A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in the memory accesses needed to fill the stream buffer. The buffer system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access, and so the access time seen by the CPU is shorter.

Abstract: System for testing memory associated with a set of check bits in an EDC system. The circuitry of the invention includes an EDC circuit; multiplexers; and a memory with first storage bits, second storage bits, and third storage bits. In writing data to the memory, a multi-bit data word having a first group of data bits and a second group of data bits is first received from a CPU bus. The first group of bits is written to the first storage bits. In a "normal" mode, the second group of bits is written to the second storage bits. A set of check bits are calculated by the EDC circuit and written to the third storage bits. In the "swap" mode, the second group of data bits is stored in the third storage bits. "Alternate" bits are calculated by the EDC circuit, and written to the second storage bits. In memory reads, contents of all of the storage bits are received from the memory and directed to the error detecting circuit. The contents of the first storage bits are directed to error correction circuit.

Abstract: A memory testing system for an electronic computing system includes multiple memory modules, each equipped with error detecting and correcting (EDC) circuitry, and is operable in a diagnostic test mode wherein read and write tests of the modules are performed in parallel. Each module includes a command/status register (CSR), used in identifying errors occurring in that module by capturing various signals at the time of the error. These signals include the type of error, the memory address involved in the error, the check bits of the data associated with the error, and the syndromes of the data. After pre-setting each CSR's diagnostic register, one module operates in a "target" mode, and the remaining modules operate in a "shadow" mode. The target module operates normally during read and write operations. When the target module is directed to write data to a particular address, the shadow modules write the same data to corresponding addresses in their memory banks.