Abstract: A data caching system and method includes a data store for caching data from a main memory, a primary tag array for holding tags associated with data cached in the data store, and a duplicate tag array which holds copies of the tags held in the primary tag array. The duplicate tag array is accessible by functions, such as external memory cache probes, such that the primary tag remains available to the processor core. An address translator maps virtual page addresses to physical page address. In order to allow a data caching system which is larger than a page size, a portion of the virtual page address is used to index the tag arrays and data store. However, because of the virtual to physical mapping, the data may reside in any of a number of physical locations. During an internally-generated memory access, the virtual address is used to look up the cache. If there is a miss, other combinations of values are substituted for the virtual bits of the tag array index.

Abstract: In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache.

Abstract: In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical address output from the translation buffer 30 are passed to a cache 28 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ, in that the memory is capable of handling other requests while a higher priority "miss" is pending.

Abstract: A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing.

Abstract: In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

Abstract: In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses error correction code (ECC) hardware to ensure the integrity of the data delivered between the cache and main memory. The prevent the ECC hardware from slowing the overall operation of the CPU, the error correction is performed underneath a write back operation.

Abstract: A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information.