Abstract: Apparatus and methods for temperature compensation of variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array, an array biasing circuit that biases cells of the variable capacitor array to control the array's capacitance, and a bias voltage level control circuit that generates one or more temperature dependent bias voltages used by the array biasing circuit to bias the variable capacitor array's cells. The bias voltage level control circuit controls the one or more temperature dependent bias voltages to change with temperature so as to compensate the variable capacitor array for changes to capacitance arising from temperature variation.

Abstract: Apparatus and methods for temperature compensation of variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array, an array biasing circuit that biases cells of the variable capacitor array to control the array's capacitance, and a bias voltage level control circuit that generates one or more temperature dependent bias voltages used by the array biasing circuit to bias the variable capacitor array's cells. The bias voltage level control circuit controls the one or more temperature dependent bias voltages to change with temperature so as to compensate the variable capacitor array for changes to capacitance arising from temperature variation.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

Abstract: An integrated circuit, such as a memory device, includes a built-in repair circuit. The repair circuit includes an on-chip source that produces a programming signal of sufficient duration and magnitude to program a programmable element that normally isolates a secondary circuit, such as redundant circuitry, from the remainder of the circuits on the device. Once programmed, the redundant circuitry may take the place of failed circuitry, and thus repair the device.

Abstract: A driver circuit for driving signal lines of a matrix type display device includes pulsewidth modulation processing circuitry for generating pulsewidth modulated video data and driver circuitry for driving the signal lines in accordance with the pulsewidth modulated video data.

Abstract: An integrated circuit, such as a memory device, includes a built-in repair circuit. The repair circuit includes an on-chip source that produces a programming signal of sufficient duration and magnitude to program a programmable element that normally isolates a secondary circuit, such as redundant circuitry, from the remainder of the circuits on the device. Once programmed, the redundant circuitry may take the place of failed circuitry, and thus repair the device.

Abstract: A current controlled field emission display includes a controller that provides a pair of pulsed clocking signals that allows current to flow from ground potential to an emitter in the field emission display during each clocking signal pulse. The number of electrons, and thus the intensity of the light will depend upon the number N of clocking signal pulses during an activation interval. In one embodiment, each of the pulsed signals includes a number N of pulses that corresponds to a desired intensity of pixels. The pulsed signals are formed by gating a clock signal in response to digital data applied to the display such that the transfer of electrons is controlled directly by the digital data. In another embodiment, the pulsed signals are produced by comparing a decoded image signal to counts from a high speed counter.

Abstract: Apparatus for ensuring that, in a portable, battery-powered communication package incorporating at least two communication devices, such as a combination cellular telephone and a pager, sufficient power is provided for extended operation of the communication device having the lowest continuous power consumption requirements when the device having a higher continuous power consumption rate has consumed a selected portion of the total power initially available to the combined devices.

Abstract: An integrated circuit, such as a memory device, includes a built-in repair circuit. The repair circuit includes an on-chip source that produces a programming signal of sufficient duration and magnitude to program a programmable element that normally isolates a secondary circuit, such as redundant circuitry, from the remainder of the circuits on the device. Once programmed, the redundant circuitry may take the place of failed circuitry, and thus repair the device.

Abstract: A current controlled field emission display includes a controller that provides a pair of pulsed clocking signals that allows current to flow from ground potential to an emitter in the field emission display during each clocking signal pulse. The number of electrons, and thus the intensity of the light will depend upon the number N of clocking signal pulses during an activation interval. In one embodiment, each of the pulsed signals includes a number N of pulses that corresponds to a desired intensity of pixels. The pulsed signals are formed by gating a clock signal in response to digital data applied to the display such that the transfer of electrons is controlled directly by the digital data. In another embodiment, the pulsed signals are produced by comparing a decoded image signal to counts from a high speed counter.

Abstract: A current controlled field emission display includes a controller that provides a pair of pulsed clocking signals that allows current to flow from ground potential to an emitter in the field emission display during each clocking signal pulse. The number of electrons, and thus the intensity of the light will depend upon the number N of clocking signal pulses during an activation interval. In one embodiment, each of the pulsed signals includes a number N of pulses that corresponds to a desired intensity of pixels. The pulsed signals are formed by gating a clock signal in response to digital data applied to the display such that the transfer of electrons is controlled directly by the digital data. In another embodiment, the pulsed signals are produced by comparing a decoded image signal to counts from a high speed counter.

Abstract: An integrated circuit, such as a memory device, includes a built-in repair circuit. The repair circuit includes an on-chip source that produces a programming signal of sufficient duration and magnitude to program a programmable element that normally isolates a secondary circuit, such as redundant circuitry, from the remainder of the circuits on the device. Once programmed, the redundant circuitry may take the place of failed circuitry, and thus repair the device.