Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Abstract: A memory system may store temperature exception tracking in a temperature log, which may be separate from data to which the temperature information corresponds. A memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Abstract: In some implementations, a memory device may detect that data is to be written for a set of temperature profiles. The memory device may write, at respective temperatures corresponding to the set of temperature profiles, multiple copies of the data. The memory device may receive, from a host device, a read request associated with the data. The memory device may detect, based on receiving the read request, a current temperature of the memory device. The memory device may read a copy, from the multiple copies, that is associated with a temperature profile, from the set of temperature profiles, that corresponds to the current temperature of the memory device. The memory device may provide, to the host device, the copy of the data.

Abstract: Methods, systems, and devices for a read status command to obtain channel state are described. In some examples, a boot sequence may be initiated at a controller of a memory system based on receiving a power signal, and a first request for status information may be transmitted from the controller to a memory device of the memory system. The controller may receive an indication of an initialization status from the memory device, and configure a channel interface for communicating with the memory device based on the indication of the initialization status. Data may subsequently be communicated between the controller and the memory device using the channel interface.

Abstract: Various aspects of the present disclosure relate to enabling a memory system to support compressing entries of a change log and improving the efficiency of the memory system by enabling the memory system changes associated with the change log to occur concurrently. Either a “staged” compression technique or a “direct” compression technique may be used to compress entries of the change log. In the case of a staged compression, the memory system may merge a new entry with a staged entry, may update the previously-staged entry, and may subsequently release the merged entry to the change log. In the case of a direct compression, the memory system may decide whether the backend entry can be directly merged with existing entries of the change log.

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device. The processing device can provide, to a host system, usable capacity information and supported logical address granularity information for the logical address space. The processing device can obtain, from the host system, a logical address granularity configuration for a partition of the logical address space. The processing device can provide, to the host system, an acknowledgement of receipt of the logical address granularity configuration.

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

Abstract: In accordance with examples as described herein, a memory system may initialize a data optimization operation by transmitting signaling to a host system. For example, the memory system may identify data associated with non-sequential logical block addresses (LBAs), and may indicate the discontinuous LBAs to the host system. In response, the host system may indicate which of the discontinuous LBAs represent sequential data. Accordingly, the memory system may sequentialize the one or more of the discontinuous LBAs to defragment the associated data.

Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.

Abstract: Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device. The processing device can provide, to a host system, usable capacity information and supported logical address granularity information for the logical address space. The processing device can obtain, from the host system, a logical address granularity configuration for a partition of the logical address space. The processing device can provide, to the host system, an acknowledgement of receipt of the logical address granularity configuration.

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including obtaining, from a host system, a power safety configuration for a partition, wherein the power safety configuration for the partition configures the memory device to implement power safe writing for the partition by operating in a first write mode utilizing single level cell (SLC) caching, or to implement non-power safe writing for the partition by operating in a second write mode without utilizing SLC caching, and configuring the memory device to operate in the first write mode or the second write mode based on the power safety configuration.

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Methods, systems, and devices for valid data identification for garbage collection are described. In connection with writing data to a block of memory cells, a memory system may identify a portion of a logical address space that includes a logical address for the data. The memory system may set a bit of a bitmap, which may indicate that the block includes data having a logical address within a portion of the logical address space corresponding to the bit. The logical address space may be divided into any quantity of portions, each corresponding to a different subset of a logical-to-physical (L2P) table, and the bitmap may include any quantity of corresponding bits. To perform garbage collection on the block, the bitmap may be used to identify one or more subsets of the L2P table to evaluate to determine whether different sets of data within the block are valid or invalid.

Abstract: In some implementations, a memory apparatus may compress a physical page table associated with a logical-to-physical (L2P) table, to obtain a compressed version of the physical page table, wherein the physical page table is associated with logical block address (LBA) and physical address pairs, wherein the compressed version is associated with a set of groups of LBAs and an exception list, and wherein the compressed version includes an indication of physical addresses associated with respective starting LBAs included in the set of groups and includes sequentiality indications for respective groups from the set of groups. The memory apparatus may receive, from a host system, a command indicating an LBA that is associated with the physical page table. The memory apparatus may perform a lookup operation using the compressed version of the physical page table to identify a physical address associated with the LBA.