Patents by Inventor David Addison
David Addison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11525885Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.Type: GrantFiled: May 3, 2019Date of Patent: December 13, 2022Assignee: Infineon Technologies AGInventors: Romain Ygnace, David Addison, Markus Bichl, Dian Tresna Nugraha, Andre Roger
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Patent number: 11286629Abstract: Present invention relates to a pipe (5) for stay cable and a method for tightening the pipe (5) using stressing means (10). The pipe (5) comprises a tubular shaped wall having an interior and an exterior surface, wherein stressing means (10) are provided to the exterior surface of the tubular shaped wall of the pipe (5), wherein the stressing means (10) are configured in a way to exert a compression force around the tubular shape wall of the pipe (5) longitudinally.Type: GrantFiled: April 6, 2018Date of Patent: March 29, 2022Assignee: VSL INTERNATIONAL AGInventors: Rachid Annan, David Addison, Gregory Trottet
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Publication number: 20210062530Abstract: Present invention relates to a pipe (5) for stay cable and a method for tightening the pipe (5) using stressing means (10). The pipe (5) comprises a tubular shaped wall having an interior and an exterior surface, wherein stressing means (10) are provided to the exterior surface of the tubular shaped wall of the pipe (5), wherein the stressing means (10) are configured in a way to exert a compression force around the tubular shape wall of the pipe (5) longitudinally.Type: ApplicationFiled: April 6, 2018Publication date: March 4, 2021Inventors: Rachid ANNAN, David ADDISON, Gregory TROTTET
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Patent number: 10829059Abstract: The extensible truck bed platform comprises a liner and a sliding bed for a pickup truck. The sliding bed may slide rearward on rails when the truck's tailgate is down to ease the task of loading and unlocking the truck bed. The liner fits into and couples to the cargo bed of the pickup truck. The liner covers the floor, side walls, and front wall of the bed. The sliding bed slidably couples to the liner via rail guides located on the liner and rails located on the sliding bed. The placement and spacing of the guide and rails in combination with overhangs on both the guides and rails prevent the sliding bed from moving in vertically or laterally relative to the liner but allows forward and backward movement of the sliding bed.Type: GrantFiled: January 8, 2019Date of Patent: November 10, 2020Inventors: David Addison, David J. Addison
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Patent number: 10505848Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.Type: GrantFiled: December 24, 2015Date of Patent: December 10, 2019Assignee: INTEL CORPORATIONInventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
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Publication number: 20190339360Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.Type: ApplicationFiled: May 3, 2019Publication date: November 7, 2019Inventors: Romain Ygnace, David Addison, Markus Bichl, Dian Tresna Nugraha, Andre Roger
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Patent number: 10416284Abstract: An example relates to a method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results without a second group of the FFT results.Type: GrantFiled: November 3, 2015Date of Patent: September 17, 2019Assignee: Infineon Technologies AGInventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
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Patent number: 10222470Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.Type: GrantFiled: November 3, 2015Date of Patent: March 5, 2019Assignee: Infineon Technologies AGInventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
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Publication number: 20190014762Abstract: A fishing rod shaft having a line guide body, e.g., a rod tip body and/or a middle line guide body designed to minimize snag locations and that facilitate exiting of fishing line wound around the shaft by flicking the rod in a casting-type motion. The outer surface of the bodies define a line opening for receiving fishing line. The line opening communicates with a line passageway. The outer surface defines a continuous, smooth, uninterrupted surface from the attached end to the terminal end but for the line opening. The line opening and the line passageway preferably define the only path to an exit orifice and the line passageway between the line opening and the exit orifice is continuous and defines no openings. The described configuration eliminates snag locations for a fishing hook or for fishing line except for the openings of the line passageway.Type: ApplicationFiled: July 9, 2018Publication date: January 17, 2019Inventors: JOSHUA M. DENTON, SHAW FURUKAWA, JOE LU, WILLIAM DAVID ADDISON, JR.
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Patent number: 9852107Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node.Type: GrantFiled: December 24, 2015Date of Patent: December 26, 2017Assignee: INTEL CORPORATIONInventors: Keith Underwood, Charles F. Giefer, David Addison
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Patent number: 9841497Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.Type: GrantFiled: June 5, 2014Date of Patent: December 12, 2017Assignee: Infineon Technologies AGInventors: Andre Roger, Romain Ygnace, David Addison
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Publication number: 20170185563Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Applicant: Intel CorporationInventors: Keith Underwood, Charles F. Giefer, David Addison
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Publication number: 20170187630Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
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Publication number: 20160131743Abstract: An example relates to a method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results without a second group of the FFT results.Type: ApplicationFiled: November 3, 2015Publication date: May 12, 2016Inventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
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Publication number: 20160131744Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.Type: ApplicationFiled: November 3, 2015Publication date: May 12, 2016Inventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
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Publication number: 20150355319Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.Type: ApplicationFiled: June 5, 2014Publication date: December 10, 2015Inventors: Andre Roger, Romain Ygnace, David Addison
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Patent number: 9118351Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.Type: GrantFiled: March 26, 2012Date of Patent: August 25, 2015Assignee: Infineon Technologies AGInventors: Antonio Vilela, Rainer Faller, Michael Goessel, Simon Brewerton, Glenn Ashley Farrall, Neil Stuart Hastie, Boyko Traykov, David Addison, Klaus Oberlaender, Thomas Rabenalt
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Publication number: 20130212441Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.Type: ApplicationFiled: March 26, 2012Publication date: August 15, 2013Applicant: Infineon Technologies AGInventors: Antonio Vilela, Rainer Faller, Michael Goessel, Simon Brewerton, Glenn Ashley Farrall, Neil Stuart Hastie, Boyko Traykov, David Addison, Klaus Oberlaender, Thomas Rabenalt
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Patent number: D891575Type: GrantFiled: May 13, 2019Date of Patent: July 28, 2020Assignee: W.C. Bradley/Zebco Holdings, Inc.Inventors: Shaw Furukawa, William David Addison, Jr., Amanda Hathcoat
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Patent number: D891576Type: GrantFiled: May 13, 2019Date of Patent: July 28, 2020Assignee: W.C. Bradley/Zebco Holdings, Inc.Inventors: Shaw Furukawa, William David Addison, Jr., Amanda Hathcoat