Abstract: Methods and apparatus for detecting false alarms are disclosed. An indication may be received that a sensor device has changed state. Data indicative of movement of the sensor device may also be received. Based on the received data indicative of movement of the sensor device, it may be determined whether the movement of the sensor device is abnormal. Based on the changed state of the sensor device and based on determining that the movement of the sensor device is abnormal, an indication of a false alarm may be caused to be output.

Abstract: Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Abstract: Some aspects of the present disclosure relate a radar system including a radio frequency (RF) receiver that receives radar data on a plurality of receive antennas. A fast Fourier transform (FFT) circuit is coupled to the RF receiver. The FFT circuit performs a FFT on the radar data to provide a plurality of Range-Doppler coordinate pairs that pertain to the plurality of receive antennas. An integration block is coupled to the FFT circuit, and sums multiple Range-Doppler coordinate pairs for respective Doppler bins to provide a plurality of Range-Doppler sums. The integration block also sums multiple Range-Doppler sums within the plurality of Range-Doppler sums to provide an integration result. The multiple Range-Doppler coordinate pairs that are summed are spaced apart from one another by a Doppler offset.

Abstract: Some aspects of the present disclosure relate to baseband processor for radar. The baseband processor includes a Doppler fast Fourier transform (FFT) circuit having an input and an output. An integration circuit has an input coupled to the output of the Doppler FFT circuit. A target detection circuit has an input coupled to an output of the integration circuit. The Doppler FFT circuit, the integration circuit, and the target detection circuit are each disposed on a silicon substrate, and the target detection circuit is arranged in series with the integration circuit and in series with the target detection circuit.

Abstract: A baseband processor including a fast Fourier transform (FFT) circuit having an FFT input and an FFT output. A first processing path having a first processing path input and a first processing path output. The first processing path including a memory coupled to the FFT output and the first processing path input via a first bus. A Direct Memory Access (DMA) coupled between the memory and the first processing path output. The DMA coupled to the memory via a second bus. A second processing path arranged in parallel with the first processing path. The second processing path including a detection circuit having a detection circuit input coupled to the FFT output and having a detection circuit output coupled to the DMA.

Abstract: A radar system includes a radio frequency (RF) receiver configured to receive radar data at a plurality of receive antennae. A fast Fourier transform (FFT) circuit is coupled to the RF receiver. The FFT circuit is configured to perform a FFT on the radar data to provide a stream of complex values. The stream of complex values includes a plurality of Range-Doppler coordinate pairs that pertain to the plurality of receive antennae. A memory is coupled to the FFT circuit. The memory is configured to store three-dimensional (3D) radar data. A Direct Memory Access circuit (DMA) is coupled to the memory.

Abstract: A radar system including a direct memory access (DMA). The DMA includes a bus interface including control/status registers and data-in/data-out registers. The DMA also includes potential object queue memory coupled to the bus interface, and a potential object queue logic coupled to the potential object queue memory. The DMA also includes boundary checking circuitry configured to detect whether any portion of a DMA read configuration is greater than a maximum range bin or less than a minimum range bin. The boundary checking circuitry detects whether any portion of the DMA read configuration is greater than a maximum Doppler bin or less than a minimum Doppler bin.

Abstract: Systems, methods, and circuitry are provided for a sorting array. In one example, a sorting array element includes an output register and control circuitry. The output register is configured to store an output value. In response to a cell under test (CUT) load signal the output register stores a CUT value and in response to a first register shift signal from a previous sorting array element the output register stores contents of an output register of the previous sorting array element. The control circuitry is configured to generate the CUT load signal and a second register shift signal for a subsequent sorting array element based on relative magnitudes of the CUT value, the output value, and an output value stored in the output register of the previous sorting array element.

Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.

Abstract: Present invention relates to a pipe (5) for stay cable and a method for tightening the pipe (5) using stressing means (10). The pipe (5) comprises a tubular shaped wall having an interior and an exterior surface, wherein stressing means (10) are provided to the exterior surface of the tubular shaped wall of the pipe (5), wherein the stressing means (10) are configured in a way to exert a compression force around the tubular shape wall of the pipe (5) longitudinally.

Abstract: Present invention relates to a pipe (5) for stay cable and a method for tightening the pipe (5) using stressing means (10). The pipe (5) comprises a tubular shaped wall having an interior and an exterior surface, wherein stressing means (10) are provided to the exterior surface of the tubular shaped wall of the pipe (5), wherein the stressing means (10) are configured in a way to exert a compression force around the tubular shape wall of the pipe (5) longitudinally.

Abstract: The extensible truck bed platform comprises a liner and a sliding bed for a pickup truck. The sliding bed may slide rearward on rails when the truck's tailgate is down to ease the task of loading and unlocking the truck bed. The liner fits into and couples to the cargo bed of the pickup truck. The liner covers the floor, side walls, and front wall of the bed. The sliding bed slidably couples to the liner via rail guides located on the liner and rails located on the sliding bed. The placement and spacing of the guide and rails in combination with overhangs on both the guides and rails prevent the sliding bed from moving in vertically or laterally relative to the liner but allows forward and backward movement of the sliding bed.

Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.

Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.

Abstract: An example relates to a method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results without a second group of the FFT results.

Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.

Abstract: A fishing rod shaft having a line guide body, e.g., a rod tip body and/or a middle line guide body designed to minimize snag locations and that facilitate exiting of fishing line wound around the shaft by flicking the rod in a casting-type motion. The outer surface of the bodies define a line opening for receiving fishing line. The line opening communicates with a line passageway. The outer surface defines a continuous, smooth, uninterrupted surface from the attached end to the terminal end but for the line opening. The line opening and the line passageway preferably define the only path to an exit orifice and the line passageway between the line opening and the exit orifice is continuous and defines no openings. The described configuration eliminates snag locations for a fishing hook or for fishing line except for the openings of the line passageway.

Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node.