Patents by Inventor David Addison

David Addison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11525885
    Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Romain Ygnace, David Addison, Markus Bichl, Dian Tresna Nugraha, Andre Roger
  • Patent number: 11286629
    Abstract: Present invention relates to a pipe (5) for stay cable and a method for tightening the pipe (5) using stressing means (10). The pipe (5) comprises a tubular shaped wall having an interior and an exterior surface, wherein stressing means (10) are provided to the exterior surface of the tubular shaped wall of the pipe (5), wherein the stressing means (10) are configured in a way to exert a compression force around the tubular shape wall of the pipe (5) longitudinally.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: March 29, 2022
    Assignee: VSL INTERNATIONAL AG
    Inventors: Rachid Annan, David Addison, Gregory Trottet
  • Publication number: 20210062530
    Abstract: Present invention relates to a pipe (5) for stay cable and a method for tightening the pipe (5) using stressing means (10). The pipe (5) comprises a tubular shaped wall having an interior and an exterior surface, wherein stressing means (10) are provided to the exterior surface of the tubular shaped wall of the pipe (5), wherein the stressing means (10) are configured in a way to exert a compression force around the tubular shape wall of the pipe (5) longitudinally.
    Type: Application
    Filed: April 6, 2018
    Publication date: March 4, 2021
    Inventors: Rachid ANNAN, David ADDISON, Gregory TROTTET
  • Patent number: 10829059
    Abstract: The extensible truck bed platform comprises a liner and a sliding bed for a pickup truck. The sliding bed may slide rearward on rails when the truck's tailgate is down to ease the task of loading and unlocking the truck bed. The liner fits into and couples to the cargo bed of the pickup truck. The liner covers the floor, side walls, and front wall of the bed. The sliding bed slidably couples to the liner via rail guides located on the liner and rails located on the sliding bed. The placement and spacing of the guide and rails in combination with overhangs on both the guides and rails prevent the sliding bed from moving in vertically or laterally relative to the liner but allows forward and backward movement of the sliding bed.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: November 10, 2020
    Inventors: David Addison, David J. Addison
  • Patent number: 10505848
    Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
  • Publication number: 20190339360
    Abstract: A radar device is disclosed that includes an input DMA module, at least one processing module, a histogram module, and an output DMA module. The input DMA module is configured to access a memory and supply data from the memory to the at least one processing module and/or to the histogram module. Each of the processing modules is configured to be enabled or disabled, wherein the at least one processing module that is enabled is configured to process at least a portion of the data supplied by the input DMA module, wherein the histogram module is fed by data from the at least processing module that is enabled and/or by the input DMA module. The output DMA module is configured to store the data that are processed by the at least one processing module that is enabled in the memory. Also, an according method is provided.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 7, 2019
    Inventors: Romain Ygnace, David Addison, Markus Bichl, Dian Tresna Nugraha, Andre Roger
  • Patent number: 10416284
    Abstract: An example relates to a method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results without a second group of the FFT results.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
  • Patent number: 10222470
    Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 5, 2019
    Assignee: Infineon Technologies AG
    Inventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
  • Publication number: 20190014762
    Abstract: A fishing rod shaft having a line guide body, e.g., a rod tip body and/or a middle line guide body designed to minimize snag locations and that facilitate exiting of fishing line wound around the shaft by flicking the rod in a casting-type motion. The outer surface of the bodies define a line opening for receiving fishing line. The line opening communicates with a line passageway. The outer surface defines a continuous, smooth, uninterrupted surface from the attached end to the terminal end but for the line opening. The line opening and the line passageway preferably define the only path to an exit orifice and the line passageway between the line opening and the exit orifice is continuous and defines no openings. The described configuration eliminates snag locations for a fishing hook or for fishing line except for the openings of the line passageway.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 17, 2019
    Inventors: JOSHUA M. DENTON, SHAW FURUKAWA, JOE LU, WILLIAM DAVID ADDISON, JR.
  • Patent number: 9852107
    Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: Keith Underwood, Charles F. Giefer, David Addison
  • Patent number: 9841497
    Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 12, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andre Roger, Romain Ygnace, David Addison
  • Publication number: 20170185563
    Abstract: Techniques are disclosed for algorithmic mapping of logical process identifiers in order to provide highly-scalable end-point addressing in multi-node systems capable of performing massively parallel applications. In particular, nodes initiating inter-process communication with a target process may use an initiator-side translation process that performs an algorithmic mapping to translate a logical process identifier (e.g., a rank/processing element) into a target physical node identifier and a target local process identifier. The initiating node may then use hardware fabric of a multi-node network to route the inter-process communication to an appropriate node. A node may receive an inter-process communication and may use a target-side translation process in hardware to translate the target virtual process identifier into a local process identifier for the node.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corporation
    Inventors: Keith Underwood, Charles F. Giefer, David Addison
  • Publication number: 20170187630
    Abstract: Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Keith D. Underwood, Charles A. Giefer, David Addison, Nathan S. Miller, Karl P. Brummel, Stephanie L. Hirnak, Eric R. Borch
  • Publication number: 20160131743
    Abstract: An example relates to a method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results without a second group of the FFT results.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 12, 2016
    Inventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
  • Publication number: 20160131744
    Abstract: A method for processing radar signals, wherein said radar signals comprise digitized data received by at least one radar antenna, the method comprising (i) determining FFT results based on the digitized data received; and (ii) storing a first group of the FFT results, wherein the first group of FFT results comprises at least two portions, wherein a first portion of FFT results is stored with a first accuracy and a second portion of FFT results is stored with a second accuracy.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 12, 2016
    Inventors: David Addison, Dian Tresna Nugraha, Andre Roger, Romain Ygnace
  • Publication number: 20150355319
    Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Andre Roger, Romain Ygnace, David Addison
  • Patent number: 9118351
    Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: August 25, 2015
    Assignee: Infineon Technologies AG
    Inventors: Antonio Vilela, Rainer Faller, Michael Goessel, Simon Brewerton, Glenn Ashley Farrall, Neil Stuart Hastie, Boyko Traykov, David Addison, Klaus Oberlaender, Thomas Rabenalt
  • Publication number: 20130212441
    Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
    Type: Application
    Filed: March 26, 2012
    Publication date: August 15, 2013
    Applicant: Infineon Technologies AG
    Inventors: Antonio Vilela, Rainer Faller, Michael Goessel, Simon Brewerton, Glenn Ashley Farrall, Neil Stuart Hastie, Boyko Traykov, David Addison, Klaus Oberlaender, Thomas Rabenalt
  • Patent number: D891575
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 28, 2020
    Assignee: W.C. Bradley/Zebco Holdings, Inc.
    Inventors: Shaw Furukawa, William David Addison, Jr., Amanda Hathcoat
  • Patent number: D891576
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 28, 2020
    Assignee: W.C. Bradley/Zebco Holdings, Inc.
    Inventors: Shaw Furukawa, William David Addison, Jr., Amanda Hathcoat