Abstract: A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. The switch can comprise a FET device and a compensation circuit coupled to the FET device to replicate and compensate for the FET device leakage, such that the switch appears not to leak current. The compensation circuit may comprise a sense device which acts as a scaled replica of the FET device being compensated. The sense device's leakage current can then be measured, reproduced at the scale factor, and injected back to the drain terminal of the FET device.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface and a plurality of pairs of conductive layers over the horizontal main surface. Different ones of the pairs are separated by different vertical distances such that each pair serves as an arcing electrode pair and different ones of the arcing electrode pairs are configured to arc discharge at different voltages.

Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap array includes a sheet resistor and an array of arcing electrode pairs formed over a substrate. The array of arcing electrode pairs includes first arcing electrodes formed on the sheet resistor and a second arcing electrode arranged as a sheet formed over the first arcing electrodes and separated from the first arcing electrodes by an arcing gap. The first arcing electrodes and second arcing electrode are electrically connected to first and second voltage nodes, respectively, and the arcing electrode pairs are configured to generate arc discharges in response to an EOS voltage signal received between the first and second voltage nodes.

Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap device includes first and second conductive layers formed over a substrate, where the first and second conductive layers are electrically connected to first and second voltage nodes, respectively. The first conductive layer includes a plurality of arcing tips configured to form arcing electrode pairs with the second conductive layer to form an arc discharge in response to an EOS voltage between the first and second voltage nodes. The spark gap device further includes a series ballast resistor electrically connected between the arcing tips and the first voltage node, where the ballast resistor in formed in a metallization layer over the substrate and a resistance of the series ballast resistor is substantially higher than a resistance of the second conductive layer.

Abstract: Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, a first conductive layer and a second conductive layer each extending over the substrate and substantially parallel to the horizontal main surface while being separated in a vertical direction crossing the horizontal main surface. One of the first and second conductive layers is electrically connected to a first voltage node and the other of the first and second conductive layers is electrically connected to a second voltage node. The first and second conductive layers serve as one or more arcing electrode pairs and have overlapping portions configured to generate one or more arc discharges extending generally in the vertical direction in response to an EOS voltage signal received between the first and second voltage nodes.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically are in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.

Abstract: Microelectromechanical systems (MEMS) switches are disclosed. Parallel configurations of back-to-back MEMS switches are disclosed in some embodiments. An isolation connection of constant electrical potential may be made to a midpoint of the back-to-back switches. In some embodiments, a separate MEMS switch is provided as a shunt switch for the main MEMS switch. MEMS switch device configurations having multiple switchable signal paths each coupling a common input electrode to a respective output electrode are also disclosed. The MEMS switch device includes shunt switches each coupling a respective output electrode to a reference potential. The presence of a shunt switch coupled to an output electrode enhances the isolation of the signal path corresponding to that output electrode when the path is open.

Abstract: A signal driver system can include one or more force amplifiers configured to provide drive signals to an output node, such as a device under test (DUT) node. The system can include a first switch circuit coupled between a first force amplifier and the output node, and the first switch circuit can include multiple parallel instances of switch circuits with respective different resistance characteristics. The system can include a second switch circuit coupled between a second force amplifier and the output node. The system can include a control circuit configured to control the switch circuit instances of the first switch circuit to mitigate glitch at the output node, for example, when switching between the first and second drive signals.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.

Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Abstract: Methods, apparatus, and processor-readable storage media for determining candidates for circuit breaker patterns in cloud applications using machine learning techniques are provided herein.