Patents by Inventor David Alan Fick

David Alan Fick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10255551
    Abstract: An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 9, 2019
    Assignees: The Regents of The University of Michigan, Mythic, Inc.
    Inventors: David Alan Fick, Laura E. Fick, Skylar J. Skrzyniarz, Manar El-Chammas
  • Publication number: 20180247192
    Abstract: An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 30, 2018
    Inventors: David Alan FICK, Laura E. FICK, Skylar J. SKRZYNIARZ, Manar EL-CHAMMAS
  • Patent number: 9760533
    Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: September 12, 2017
    Assignee: THE REGENTS ON THE UNIVERSITY OF MICHIGAN
    Inventors: Laura Fick, David T. Blaauw, Dennis Sylvester, Michael B. Henry, David Alan Fick
  • Patent number: 9490779
    Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 8, 2016
    Assignee: The Regents of the University of Michigan
    Inventors: Bharan Giridhar, Matthew Rudolph Fojtik, David Alan Fick, Dennis Michael Sylvester, David Theodore Blaauw
  • Publication number: 20160291129
    Abstract: A matched filter is provided for signal processing applications such as GNSS and RADAR. The filter includes a plurality of correlator cells configured to receive a digital signal and are arranged so that values of the digital signal can be shifted amongst the plurality of correlator cells. Each correlator cell includes a correlator circuit, a data source and a current source. The correlator circuit is configured to receive a value from the digital signal and operates to correlate the value with a value of the known pattern stored in the data store. The current source is interfaced with the correlator circuit and selectively sources current based on the correlation operation performed by the correlator circuit; and an output circuit is coupled to each of the plurality of correlator cell and operates to generate an output which is correlated to current that is being source collectively by the current sources.
    Type: Application
    Filed: February 9, 2015
    Publication date: October 6, 2016
    Inventors: Michael B. HENRY, Dennis SYLVESTER, Bharan GIRIDHAR, David T. BLAAUW, Laura FREYMAN, David Alan FICK
  • Patent number: 9335972
    Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: May 10, 2016
    Assignee: The Regents of the University of Michigan
    Inventors: Kaiyuan Yang, Dennis Michael Sylvester, David Theodore Blaauw, David Alan Fick, Michael B. Henry, Yoonmyung Lee
  • Publication number: 20160048755
    Abstract: A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 18, 2016
    Inventors: Laura Freyman, David T. Blaauw, Dennis Sylvester, Michael B. Henry, David Alan Fick
  • Publication number: 20150154006
    Abstract: A true random number generator comprises a ring oscillator which is triggered to start oscillating in a first mode of oscillation at an oscillation start time. The first mode of oscillation will eventually collapse to a second mode of oscillation dependent on thermal noise. A collapse time from the oscillation start time to the time at which the oscillator collapses to the second mode is measured, and this can be used to determine a random number. The TRNG can be synthesized entirely using standard digital techniques and is able to provide high randomness, good throughput and energy efficiency.
    Type: Application
    Filed: November 29, 2013
    Publication date: June 4, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Kaiyuan YANG, Dennis Michael Sylvester, David Theodore Blaauw, David Alan Fick, Michael B. Henry, Yoonmyung Lee
  • Publication number: 20150015305
    Abstract: Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 15, 2015
    Inventors: Bharan GIRIDHAR, Matthew Rudolph Fojtik, David Alan Fick, Dennis Michael Sylvester, David Theodore Blaauw
  • Patent number: 8407025
    Abstract: An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: March 26, 2013
    Assignees: ARM Limited, The Regents of the University of Michigan
    Inventors: David Theodore Blaauw, Dennis Michael Sylvester, David Alan Fick, Stuart David Biles, Michael John Wieckowski, Scott McLean Hanson, Gregory Kengho Chen
  • Patent number: 8276014
    Abstract: A data processing circuitry for processing data is disclosed.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 25, 2012
    Assignee: The Regents of the University of Michigan
    Inventors: Matthew Rudolph Fojtik, Dennis Michael Sylvester, David Theodore Blaauw, David Alan Fick
  • Publication number: 20110202786
    Abstract: A data processing circuitry for processing data is disclosed.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 18, 2011
    Applicant: The Regents of the University of Michigan
    Inventors: Matthew Rudolph Fojtik, Dennis Michael Sylvester, David Theodore Blaauw, David Alan Fick
  • Publication number: 20100217562
    Abstract: An apparatus for processing data 2 is provided with a time-to-digital converter 18 which serves to measure signal processing delay through one or more signal paths through a processing stage. This measured delay generates a delay value representing a plurality of instances of the signal processing delay which have been measured. Analysis is performed under software control to estimate a worst case signal processing delay through the processing stage based upon the delay values which have been generated. An adjustment of the operating parameters, such as supply voltage and clock frequency, of the apparatus is made to provide a timing margin through the processing stage sufficient to satisfy the worst case signal processing delay which has been estimated without an excessive margin.
    Type: Application
    Filed: February 25, 2009
    Publication date: August 26, 2010
    Inventors: David Theodore Blaauw, Dennis Michael Sylvester, David Alan Fick, Stuart David Biles, Michael John Wieckowski, Scott McLean Hanson, Gregory Kengho Chen