Patents by Inventor David Albert Carlson
David Albert Carlson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11507379Abstract: A front-end portion of a pipeline includes a stage that speculatively issues at least some instructions out-of-order. A back-end portion of the pipeline includes one or more stages that access a processor memory system. In the front-end (back-end), execution of instructions is managed based on information available in the front-end (back-end). Managing execution of a first memory barrier instruction includes preventing speculative out-of-order issuance of store instructions. The back-end control circuitry provides information accessible to the front-end control circuitry indicating that one or more particular memory instructions have completed handling by the processor memory system.Type: GrantFiled: May 31, 2019Date of Patent: November 22, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson
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Patent number: 11327759Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.Type: GrantFiled: September 25, 2018Date of Patent: May 10, 2022Assignee: Marvell Asia Pte, Ltd.Inventors: David Albert Carlson, Shubhendu Sekhar Mukherjee, Michael Bertone, David Asher, Daniel Dever, Bradley D. Dobbie, Thomas Hummel
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Patent number: 11176055Abstract: A pipeline in a processor core includes: at least one stage that decodes instructions including load instructions that retrieve data stored at respective virtual addresses, at least one stage that issues at least some decoded load instructions out-of-order, and at least one stage that initiates at least one prefetch operation. Copies of page table entries mapping virtual addresses to physical addresses are stored in a TLB. Managing misses in the TLB includes: handling a load instruction issued out-of-order using a hardware page table walker, after a miss in the TLB, handling a prefetch operation using the hardware page table walker, after a miss in the TLB, and handling any software-calling faults triggered by out-of-order load instructions handled by the hardware page table walker differently from any software-calling faults triggered by prefetch operations handled by the hardware page table walker.Type: GrantFiled: August 6, 2019Date of Patent: November 16, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
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Publication number: 20210011729Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.Type: ApplicationFiled: September 29, 2020Publication date: January 14, 2021Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
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Publication number: 20200379772Abstract: A front-end portion of a pipeline includes a stage that speculatively issues at least some instructions out-of-order. A back-end portion of the pipeline includes one or more stages that access a processor memory system. In the front-end (back-end), execution of instructions is managed based on information available in the front-end (back-end). Managing execution of a first memory barrier instruction includes preventing speculative out-of-order issuance of store instructions. The back-end control circuitry provides information accessible to the front-end control circuitry indicating that one or more particular memory instructions have completed handling by the processor memory system.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson
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Patent number: 10817300Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.Type: GrantFiled: October 26, 2018Date of Patent: October 27, 2020Assignee: Marvell Asia Pte, Ltd.Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
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Patent number: 10747543Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.Type: GrantFiled: December 28, 2018Date of Patent: August 18, 2020Assignee: Marvell Asia Pte, Ltd.Inventors: Gerald Lampert, Nitin Prakash, Shubhendu Sekhar Mukherjee, David Albert Carlson
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Publication number: 20200210195Abstract: At least some instructions executed in a pipeline are each associated with corresponding trace information that characterizes execution of that instruction in the pipeline. A predetermined type of store instructions flow through a subset of contiguous stages of the pipeline. A signal is received to store a portion of the trace information. A stage before the subset of contiguous stages is stalled. A store instruction of the predetermined type is inserted into a stage at the beginning of the subset of contiguous stages to enable the store instruction to reach the memory access stage at which an operand of the store instruction including the portion of the trace information is sent out of the pipeline. The store instruction is filtered from a stage of the subset of contiguous stages that occurs earlier in the pipeline than a stage in which trace information is generated.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Gerald Lampert, Nitin Prakash, Shubhendu Sekhar Mukherjee, David Albert Carlson
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Publication number: 20200133680Abstract: In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Michael Bertone
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Publication number: 20200097292Abstract: Managing the messages associated with memory pages stored in a main memory includes: receiving a message from outside the pipeline, and providing at least one low-level instruction to the pipeline for performing an operation indicated by the received message. Executing instructions in the pipeline includes: executing a series of low-level instructions in the pipeline, where the series of low-level instructions includes a first (second) set of low-level instructions converted from a first (second) high-level instruction.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: David Albert Carlson, Shubhendu Sekhar MUKHERJEE, Michael BERTONE, David Asher, Daniel DEVER, Bradley D. DOBBIE, Tom HUMMEL
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Patent number: 10599577Abstract: Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of a first processor core should be admitted into the shared resource based at least in part on the stored admission control information; and updating the admission control information based on a latency of a response to a particular memory access request admitted into the shared resource, where the updating depends on whether the response originated from a particular cache level included in the shared resource or from the main memory.Type: GrantFiled: July 28, 2016Date of Patent: March 24, 2020Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson, Richard Eugene Kessler, Wilson Snyder
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Patent number: 10599430Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.Type: GrantFiled: May 31, 2017Date of Patent: March 24, 2020Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
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Patent number: 10558577Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.Type: GrantFiled: June 18, 2018Date of Patent: February 11, 2020Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, David Albert Carlson, Srilatha Manne
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Patent number: 10445096Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.Type: GrantFiled: May 31, 2017Date of Patent: October 15, 2019Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
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Patent number: 10331500Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.Type: GrantFiled: September 7, 2017Date of Patent: June 25, 2019Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
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Patent number: 10248420Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.Type: GrantFiled: May 31, 2017Date of Patent: April 2, 2019Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
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Patent number: 10223279Abstract: A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.Type: GrantFiled: June 27, 2016Date of Patent: March 5, 2019Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Michael Bertone, David Albert Carlson
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Publication number: 20180300247Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.Type: ApplicationFiled: June 18, 2018Publication date: October 18, 2018Inventors: Shubhendu Sekhar MUKHERJEE, David Albert CARLSON, Srilatha MANNE
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Publication number: 20180293114Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.Type: ApplicationFiled: September 7, 2017Publication date: October 11, 2018Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler
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Publication number: 20180293113Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.Type: ApplicationFiled: May 31, 2017Publication date: October 11, 2018Inventors: Shubhendu Sekhar Mukherjee, Isam Wadih Akkawi, David Asher, Michael Bertone, David Albert Carlson, Bradley Dobbie, Richard Eugene Kessler