Patents by Inventor David Alexander Munday

David Alexander Munday has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10725528
    Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 28, 2020
    Assignee: Altera Corporation
    Inventors: Shiva Rao, David Alexander Munday
  • Patent number: 10686449
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 16, 2020
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
  • Patent number: 10331533
    Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Matthew Harbridge Gerlach
  • Publication number: 20190155367
    Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 23, 2019
    Inventors: Shiva Rao, David Alexander Munday
  • Patent number: 10216254
    Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: February 26, 2019
    Assignee: Altera Corporation
    Inventors: Shiva Rao, David Alexander Munday
  • Publication number: 20190052274
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Application
    Filed: September 10, 2018
    Publication date: February 14, 2019
    Inventors: David Alexander Munday, Randall Carl Bilbrey, JR., Evan Custodio
  • Publication number: 20190042329
    Abstract: A system is provided that includes a host processor coupled to a programmable acceleration coprocessor. The coprocessor may include logic for implementing a physical function and multiple associated virtual functions. The coprocessor may include a static programmable resource interface circuit (PIC) configured to perform management functions and one or more partial reconfiguration regions, each of which can be loaded with an accelerator function unit (AFU). An AFU may further be partitioned into AFU contexts (AFCs), each of which can be mapped to one of the virtual functions. The PIC enables hardware discovery/enumeration and loading of device drivers such that security isolation and interface performance are maintained.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Inventors: Utkarsh Y. Kakaiya, Pratik Marolia, Joshua David Fender, Sundar Nadathur, Nagabhushan Chitlur, Yuling Yang, David Alexander Munday
  • Patent number: 10075167
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 11, 2018
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
  • Publication number: 20180203781
    Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.
    Type: Application
    Filed: December 14, 2017
    Publication date: July 19, 2018
    Inventors: David Alexander Munday, Matthew Harbridge Gerlach
  • Publication number: 20180076814
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Evan Custodio
  • Patent number: 9852040
    Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: December 26, 2017
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Matthew Harbridge Gerlach
  • Patent number: 9825635
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 21, 2017
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
  • Publication number: 20170099053
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 6, 2017
    Inventors: David Alexander Munday, Randall Carl Bilbrey, JR., Evan Custodio
  • Patent number: 9503094
    Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: November 22, 2016
    Assignee: Altera Corporation
    Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio