Patents by Inventor David Alexander Munday
David Alexander Munday has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804844Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: GrantFiled: April 11, 2022Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
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Publication number: 20220321129Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: ApplicationFiled: April 11, 2022Publication date: October 6, 2022Inventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
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Patent number: 11303279Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: GrantFiled: June 12, 2020Date of Patent: April 12, 2022Assignee: Altera CorporationInventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
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Publication number: 20210067162Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: ApplicationFiled: June 12, 2020Publication date: March 4, 2021Inventors: David Alexander Munday, Randall Carl Bilbrey, JR., Evan Custodio
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Patent number: 10725528Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: GrantFiled: January 28, 2019Date of Patent: July 28, 2020Assignee: Altera CorporationInventors: Shiva Rao, David Alexander Munday
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Patent number: 10686449Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: GrantFiled: September 10, 2018Date of Patent: June 16, 2020Assignee: Altera CorporationInventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
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Patent number: 10331533Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.Type: GrantFiled: December 14, 2017Date of Patent: June 25, 2019Assignee: Altera CorporationInventors: David Alexander Munday, Matthew Harbridge Gerlach
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Publication number: 20190155367Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: ApplicationFiled: January 28, 2019Publication date: May 23, 2019Inventors: Shiva Rao, David Alexander Munday
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Patent number: 10216254Abstract: Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.Type: GrantFiled: June 29, 2016Date of Patent: February 26, 2019Assignee: Altera CorporationInventors: Shiva Rao, David Alexander Munday
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Publication number: 20190052274Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: ApplicationFiled: September 10, 2018Publication date: February 14, 2019Inventors: David Alexander Munday, Randall Carl Bilbrey, JR., Evan Custodio
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Publication number: 20190042329Abstract: A system is provided that includes a host processor coupled to a programmable acceleration coprocessor. The coprocessor may include logic for implementing a physical function and multiple associated virtual functions. The coprocessor may include a static programmable resource interface circuit (PIC) configured to perform management functions and one or more partial reconfiguration regions, each of which can be loaded with an accelerator function unit (AFU). An AFU may further be partitioned into AFU contexts (AFCs), each of which can be mapped to one of the virtual functions. The PIC enables hardware discovery/enumeration and loading of device drivers such that security isolation and interface performance are maintained.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Inventors: Utkarsh Y. Kakaiya, Pratik Marolia, Joshua David Fender, Sundar Nadathur, Nagabhushan Chitlur, Yuling Yang, David Alexander Munday
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Patent number: 10075167Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: GrantFiled: November 20, 2017Date of Patent: September 11, 2018Assignee: Altera CorporationInventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
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Publication number: 20180203781Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.Type: ApplicationFiled: December 14, 2017Publication date: July 19, 2018Inventors: David Alexander Munday, Matthew Harbridge Gerlach
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Publication number: 20180076814Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: David Alexander Munday, Randall Carl Bilbrey, Evan Custodio
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Patent number: 9852040Abstract: This disclosure relates to techniques for updating a memory map maintained by processing circuitry that is coupled to programmable logic circuitry. One of the techniques may involve detecting reconfiguration of a device component formed on a portion of the programmable logic circuitry using monitoring circuitry. The technique may further include generating a notification event based on the reconfiguration of the device component using the monitoring circuitry. The notification event may then be sent to the processing circuitry using the monitoring circuitry. The technique may further involve updating, using the processing circuitry, the memory map based on the notification event.Type: GrantFiled: March 9, 2016Date of Patent: December 26, 2017Assignee: Altera CorporationInventors: David Alexander Munday, Matthew Harbridge Gerlach
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Patent number: 9825635Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: GrantFiled: October 27, 2016Date of Patent: November 21, 2017Assignee: Altera CorporationInventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio
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Publication number: 20170099053Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: ApplicationFiled: October 27, 2016Publication date: April 6, 2017Inventors: David Alexander Munday, Randall Carl Bilbrey, JR., Evan Custodio
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Patent number: 9503094Abstract: A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in the first area. The programmable logic fabric also includes a second area, wherein a second persona is configured to be programmed in the second area in a second persona programming time. The device is configured to be controlled by a host to switch from running the first persona to running the second persona in a time less than the second persona programming time.Type: GrantFiled: October 5, 2015Date of Patent: November 22, 2016Assignee: Altera CorporationInventors: David Alexander Munday, Randall Carl Bilbrey, Jr., Evan Custodio